diff options
| author | Brian Silver <bsilver@us.ibm.com> | 2016-06-28 13:11:09 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-07-21 17:15:48 -0400 |
| commit | a0fe75642c8e289f48153d8cb093d6776d1bd10d (patch) | |
| tree | 29196194bb314c3aac203d2cbc0fb907f8ef992c /src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | |
| parent | 872cf1dfc799619ae44b6c3561a1e9cbb5708eda (diff) | |
| download | talos-hostboot-a0fe75642c8e289f48153d8cb093d6776d1bd10d.tar.gz talos-hostboot-a0fe75642c8e289f48153d8cb093d6776d1bd10d.zip | |
Add flush, init io to phy reset
Change-Id: I592762b492eb8da0542121262ecc9a2af9e2ff3b
RTC: 156940
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26632
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26639
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index e3d47546c..a7609b3c1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -79,6 +79,15 @@ extern "C" FAPI_TRY( mss::change_resetn(i_target, mss::LOW), "change_resetn for %s failed", mss::c_str(i_target) ); // + // Flush output drivers + // + + // 8. Set FLUSH=1 and INIT_IO=1 in the DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL and DDRPHY_DP16_DATA_BIT_DIR1 register + // 9. Wait at least 32 dphy_gckn clock cycles. + // 10. Set FLUSH=0 and INIT_IO=0 in the DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL register + FAPI_TRY( mss::flush_output_drivers(i_target), "unable to flush output drivers for %s", mss::c_str(i_target) ); + + // // ZCTL Enable // @@ -140,8 +149,6 @@ extern "C" // slew cal successful // FAPI_TRY( mss::slew_cal(i_target), "slew_cal for %s failed", mss::c_str(i_target)); - FAPI_TRY( mss::ddr_phy_flush(i_target), "ddr_phy_flush failed for %s", mss::c_str(i_target) ); - #ifdef LEAVES_OUTPUT_TO_DIMM_TRISTATE // Per J. Bialas, force_mclk_low can be dasserted. FAPI_TRY(mss::change_force_mclk_low(i_target, mss::LOW), |
