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author | Brian Silver <bsilver@us.ibm.com> | 2016-06-21 12:46:42 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-06-22 14:20:13 -0400 |
commit | ff6a453ebb1ef7f89315fadcdd70bd795dbca568 (patch) | |
tree | 85269fd6e442f339aa41f997494cd53c4d9d087d /src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | |
parent | bc2f2095a281a21ab45b829e67c9f1788d5f9984 (diff) | |
download | talos-hostboot-ff6a453ebb1ef7f89315fadcdd70bd795dbca568.tar.gz talos-hostboot-ff6a453ebb1ef7f89315fadcdd70bd795dbca568.zip |
Add bang-bang lock algorithm for the PHY
Change-Id: I8a31d4105336aaeb3cbd13379024eb509a1df4f8
RTC:153954
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26095
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26098
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 55 |
1 files changed, 40 insertions, 15 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 4c3dd6ebc..7d1821b4c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -47,11 +47,6 @@ extern "C" /// fapi2::ReturnCode p9_mss_ddr_phy_reset(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) { - // Cache the name of our target. We can't just keep the pointer from c_str as - // it points to thread-local space and anything we call might change the string. - char l_name[fapi2::MAX_ECMD_STRING_LEN]; - strncpy(l_name, mss::c_str(i_target), fapi2::MAX_ECMD_STRING_LEN); - FAPI_INF("********* %s start *********", __func__); // Initialize via scoms. Could be put in to p9_mss_scominit.C if that ever exists BRS. @@ -68,32 +63,62 @@ extern "C" FAPI_DBG("All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values"); // 2. Assert reset to PHY for 32 memory clocks - FAPI_TRY( mss::change_resetn(i_target, mss::HIGH), "change_resetn for %s failed", l_name ); + FAPI_TRY( mss::change_resetn(i_target, mss::HIGH), "change_resetn for %s failed", mss::c_str(i_target) ); fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)); // 3. Deassert reset_n - FAPI_TRY( mss::change_resetn(i_target, mss::LOW), "change_resetn for %s failed", l_name ); + FAPI_TRY( mss::change_resetn(i_target, mss::LOW), "change_resetn for %s failed", mss::c_str(i_target) ); // 4, 5, 6. - FAPI_TRY( mss::toggle_zctl(i_target), "toggle_zctl for %s failed", l_name ); + FAPI_TRY( mss::toggle_zctl(i_target), "toggle_zctl for %s failed", mss::c_str(i_target) ); // 7, 8. - FAPI_TRY( mss::deassert_pll_reset(i_target), "deassert_pll_reset failed for %s", l_name ); + FAPI_INF("deassert_pll_reset for %s", mss::c_str(i_target)); + FAPI_TRY( mss::deassert_pll_reset(i_target) ); - // 9, 10, 11, 12 & 13. Lock dphy_gckn and sysclk - FAPI_TRY( mss::bang_bang_lock(i_target) ); + // + // Start bang-bang-lock + // - // 14? + // 16. Take dphy_nclk/SysClk alignment circuits out of reset and put into continuous update mode, + FAPI_INF("set up of phase rotator controls %s", mss::c_str(i_target) ); + FAPI_TRY( mss::setup_phase_rotator_control_registers(i_target, mss::ON) ); + + // 17. Wait at least 5932 dphy_nclk clock cycles to allow the dphy_nclk/SysClk alignment circuit to perform initial + // alignment. + FAPI_INF("Wait at least 5932 memory clock cycles for clock alignment circuit to perform initial alignment %s", + mss::c_str(i_target)); + FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 5932), 2000) ); + + // 18. Check for LOCK in DDRPHY_DP16_SYSCLK_PR_VALUE registers and DDRPHY_ADR_SYSCLK_PR_VALUE + FAPI_INF("Checking for bang-bang lock %s ...", mss::c_str(i_target)); + FAPI_TRY( mss::check_bang_bang_lock(i_target) ); + + // 19. Write 0b0 into the DDRPHY_PC_RESETS register bit 1. This write de-asserts the SYSCLK_RESET. + FAPI_INF("deassert sysclk reset %s", mss::c_str(i_target)); + FAPI_TRY( mss::deassert_sysclk_reset(i_target), "deassert_sysclk_reset failed for %s", mss::c_str(i_target) ); + + // 20. Write 8020h into the DDRPHY_ADR_SYSCLK_CNTL_PR Registers and + // DDRPHY_DP16_SYSCLK_PR0/1 registers This write takes the dphy_nclk/ + // SysClk alignment circuit out of the Continuous Update mode. + FAPI_INF("take sysclk alignment out of cont update mode %s", mss::c_str(i_target)); + FAPI_TRY( mss::setup_phase_rotator_control_registers(i_target, mss::OFF), + "set up of phase rotator controls failed (out of cont update) %s", mss::c_str(i_target) ); + + // 21. Wait at least 32 dphy_nclk clock cycles. + FAPI_DBG("Wait at least 32 memory clock cycles %s", mss::c_str(i_target)); + FAPI_TRY( fapi2::delay(mss::cycles_to_ns(i_target, 32), mss::cycles_to_simcycles(32)) ); // + // Done bang-bang-lock // - // + //FIXME: Need to code.. FAPI_TRY(mss_slew_cal(i_target), // "mss_slew_cal Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); // slew cal successful -// FAPI_TRY( mss::slew_cal(i_target), "slew_cal for %s failed", l_name); +// FAPI_TRY( mss::slew_cal(i_target), "slew_cal for %s failed", mss::c_str(i_target)); - FAPI_TRY( mss::ddr_phy_flush(i_target), "ddr_phy_flush failed for %s", l_name ); + FAPI_TRY( mss::ddr_phy_flush(i_target), "ddr_phy_flush failed for %s", mss::c_str(i_target) ); #ifdef LEAVES_OUTPUT_TO_DIMM_TRISTATE // Per J. Bialas, force_mclk_low can be dasserted. |