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| author | Andre Marin <aamarin@us.ibm.com> | 2017-07-16 00:56:52 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-07-27 18:00:19 -0400 |
| commit | c85d4152d28b4a9d5eb392b2025937f6965a5100 (patch) | |
| tree | 6db6ef655aeed0f279fb48c19e7a58a0d653f785 /src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | |
| parent | 74a5bd2d0006fe0b2e4511ccaae605b60b2d096d (diff) | |
| download | talos-hostboot-c85d4152d28b4a9d5eb392b2025937f6965a5100.tar.gz talos-hostboot-c85d4152d28b4a9d5eb392b2025937f6965a5100.zip | |
Added ATTR_MSS_VPD_MT_WINDAGE_RD_CTR support after SYSCLK_RESET.
Change-Id: I588b304a6694677c28196ca5161800d4ae19a21f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43173
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43174
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index a0bc1c84f..0b08a9312 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -150,6 +150,14 @@ extern "C" FAPI_TRY( mss::deassert_sysclk_reset(i_target), "deassert_sysclk_reset failed for %s", mss::c_str(i_target), "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); + // Reset the windage registers + // According to the PHY team, resetting the read delay offset must be done after SYSCLK_RESET + for( const auto& p : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target) ) + { + FAPI_TRY( mss::dp16::reset_read_delay_offset_registers(p), + "Failed reset_read_delay_offset_registers() for %s", mss::c_str(p) ); + } + // 20. Write 8020h into the DDRPHY_ADR_SYSCLK_CNTL_PR Registers and // DDRPHY_DP16_SYSCLK_PR0/1 registers This write takes the dphy_nclk/ // SysClk alignment circuit out of the Continuous Update mode. |
