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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-02-10 14:59:55 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-03-16 16:35:30 -0400 |
| commit | 3b87f474990c43edbf8180b9f4eaef189b4d2f6b (patch) | |
| tree | 9893ebf763b40d4ef892acef26ec2dc70b6425ba /src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | |
| parent | 3d2cb936a4709b34c1b43e40051a2787ed5c9836 (diff) | |
| download | talos-hostboot-3b87f474990c43edbf8180b9f4eaef189b4d2f6b.tar.gz talos-hostboot-3b87f474990c43edbf8180b9f4eaef189b4d2f6b.zip | |
Updates code to run PHY DCD calibration
This update adds in workarounds to run the PHY's
duty cycle distortion calibration algorithm in DD1.*.
Change-Id: I5e9abcf7450491995f5114c362e3ac99d517417e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36302
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36329
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 56dcdc9d7..22ae9b1ba 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -70,11 +70,6 @@ extern "C" FAPI_TRY(mss::change_force_mclk_low(i_target, mss::LOW), "force_mclk_low (set high) Failed rc = 0x%08X", uint64_t(fapi2::current_err) ); - // New for Nimbus - perform duty cycle clock distortion calibration -#ifdef RUN_DCD - FAPI_TRY( mss::adr32s::duty_cycle_distortion_calibration(i_target) ); -#endif - // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value. FAPI_TRY( mss::dp16::reset_sysclk(i_target) ); @@ -161,6 +156,10 @@ extern "C" // Workarounds FAPI_TRY( mss::workarounds::dp16::after_phy_reset(i_target) ); + // New for Nimbus - perform duty cycle clock distortion calibration (DCD cal) + // Per PHY team's characterization, the DCD cal needs to be run after DLL calibration + FAPI_TRY( mss::adr32s::duty_cycle_distortion_calibration(i_target) ); + // mss::check::during_phy_reset checks to see if there are any FIR. We do this 'twice' once here // (as part of the good-path) and once if we jump to the fapi_try label. if ((fapi2::current_err = mss::check::during_phy_reset(i_target)) != fapi2::FAPI2_RC_SUCCESS) |
