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authorAndre Marin <aamarin@us.ibm.com>2017-10-04 10:39:39 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-11-01 15:39:24 -0400
commitaa313fb234e1d00c425e2df84b59725f318d6548 (patch)
tree9af01759b9ea0a8ba66654248ea5a3966e80d0c7 /src/import/chips/p9/procedures/hwp/memory/lib
parent6b9bc4190d6086ec1384105e5579a09e1096e6c2 (diff)
downloadtalos-hostboot-aa313fb234e1d00c425e2df84b59725f318d6548.tar.gz
talos-hostboot-aa313fb234e1d00c425e2df84b59725f318d6548.zip
Update HPW Level for MSS API library
Change-Id: I33f36a6cc647d66c39ac46ba2922dcd1c49d86b5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47150 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47165 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/check.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mss_utils.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_kind.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/assert_noexit.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/bit_count.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/count_dimm.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/utils/swizzle.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C6
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H8
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.H4
61 files changed, 101 insertions, 101 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
index 694831f42..c21bc49af 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 1
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_DATA_BUFFER_DDR4_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H
index b714aaa2d..7be0ef146 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_ECC_TRAITS_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H
index fbb100ed0..35a0135b3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_MAINLINE_RCE_TRAP_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H
index 885e37596..516f9181e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_MAINLINE_UE_TRAP_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H
index 61e57869f..a06a2ccbe 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_MAINT_CURRENT_TRAP_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C
index c50c32c2a..ef49471e9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.C
@@ -27,7 +27,7 @@
///
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com>
-// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H
index ea410dd5c..793d92fc9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/attr_setters.H
@@ -29,7 +29,7 @@
///
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com>
-// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H
index d258f2c71..14ae03d36 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H
@@ -27,7 +27,7 @@
/// @file plug_rules.H
/// @brief Enforcement of rules for plugging in DIMM
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
index 36ef41af2..f2e63484c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
@@ -27,7 +27,7 @@
/// @brief Determine effective config for mss settings
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP FW Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.H
index fc82aaed1..7e4d3c96c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_CHECK_FIR_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H
index aece31060..92fc8bd7e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/fir.H
@@ -27,10 +27,10 @@
/// @file fir.H
/// @brief Memory subsystem FIR support
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_FIR_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C
index 126ab1b2b..160fef720 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C
@@ -27,10 +27,10 @@
/// @file memdiags_fir.C
/// @brief Subroutines for memdiags/prd FIR
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H
index 552b5bdcd..c3a8e6c8c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,10 +27,10 @@
/// @file memdiags_fir.H
/// @brief Subroutines for memdiags/prd FIR
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_MEMDIAGS_FIR_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C
index 284009106..153492989 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C
@@ -27,7 +27,7 @@
/// @file unmask.C
/// @brief Subroutines for unmasking and setting up MSS FIR
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H
index 116c479e6..749eb50c3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H
@@ -27,7 +27,7 @@
/// @file unmask.H
/// @brief Subroutines for unmasking and setting up MSS FIR
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
index 7fb9ecfaa..4c88f60d8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.C
@@ -28,7 +28,7 @@
/// @brief CAS latency class implementation
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H
index 7d0531aec..c4b1e82c5 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/cas_latency.H
@@ -28,7 +28,7 @@
/// @brief CAS latency class declaration
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C
index 822acde60..ef9933edb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C
@@ -27,10 +27,10 @@
/// @file perf_reg.C
/// @brief Subroutines to manipulate the memory controller performance registers
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
index 413271041..4fec3a846 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
@@ -27,10 +27,10 @@
/// @file port.C
/// @brief Subroutines to manipulate ports (phy + mc for certain operations)
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
index b6c2ece01..e7da45e66 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
@@ -27,10 +27,10 @@
/// @file port.H
/// @brief Code to support ports (phy _ mc for certain operations)
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_PORT_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
index bdee48e3c..5d8486f3d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
@@ -27,10 +27,10 @@
/// @file xlate.C
/// @brief Subroutines to manipulate the memory controller translation registers
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H
index 88019d483..7b745da9a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H
@@ -27,10 +27,10 @@
/// @file xmalte.H
/// @brief Definitions for translation registers
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_XLT_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H
index 15b63fd6a..6e24c958b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_MCBIST_ADDRESS_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C
index f97ef924e..1569d31b1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H
index 27088d4a8..b6ce6ec12 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 1
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
//
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C
index b77698190..ef65e381a 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H
index 6c9d66ea9..283cec846 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_MCBIST_SETTINGS_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C
index 9db0721ea..933676c48 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H
index a6b5b9400..5e8291a21 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_MCBIST_SIM_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
index e1a0a31fd..60c51e9ae 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
@@ -30,7 +30,7 @@
/// accessor generator. EC workarounds is one example - everytime someone creates
/// a work-around they'd be burdened with updating this file.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_utils.H
index 1ce3b427a..f29f4803b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_utils.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_utils.H
@@ -28,9 +28,9 @@
/// @brief Main include file for the Memory Subsystem
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_P9_ATTR_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
index ac45811f6..0de3f350e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_ADR32S_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
index a310cde85..797588274 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
@@ -30,7 +30,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_SEQ_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H
index f3f9c2c47..cfca24008 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H
@@ -27,9 +27,9 @@
/// @brief Decoder for ATTR_MSS_MRW_PWR_CURVE_SLOPE and _INTERCEPT and THERMAL_POWER_LIMIT
///
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_POWER_DECODER__
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index d6e5c4f53..88ec5138b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -27,10 +27,10 @@
/// @mss_const.H
/// @This file contains constants for the memory team.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_CONST_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_kind.H
index b1b6f2351..6ffea0585 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_kind.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_kind.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,10 +27,10 @@
/// @file mss_kind.H
/// @brief Implementation of mss specific types
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_KIND_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H
index bb19eaf34..85eafa8e0 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.H
@@ -27,9 +27,9 @@
/// @brief SPD factory and functions
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_SPD_FACTORY_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/assert_noexit.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/assert_noexit.H
index 04d4e4054..35f0b68d4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/assert_noexit.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/assert_noexit.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,10 +27,10 @@
/// @file assert_noexit.H
/// @brief MSS specific assert, but don't exit macro
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_ASSERT_NOEXIT_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/bit_count.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/bit_count.H
index 7db7270c5..d18adafdc 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/bit_count.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/bit_count.H
@@ -27,10 +27,10 @@
/// @file bit_count.H
/// @brief count bits
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_BIT_COUNT_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
index 18bd74c25..b18eb9b50 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/conversions.H
@@ -27,7 +27,7 @@
/// @file conversions.H
/// @brief Functions to convert units
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/count_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/count_dimm.H
index cdd09a878..530044704 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/count_dimm.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/count_dimm.H
@@ -27,7 +27,7 @@
/// @file count_dimm.H
/// @brief Count the DIMM attached to a target
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H
index b776b824e..1154694e9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,10 +27,10 @@
/// @file dump_regs.H
/// @brief Dump registers
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_DUMP_REGS_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
index a2274cc5f..cde71afd1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
@@ -27,10 +27,10 @@
/// @file fake_vpd.C
/// @brief A tool to return fake (fixed) system VPD for testing, development
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#include <mss.H>
#include <lib/utils/fake_vpd.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
index bfbd60f20..e410c67f6 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.H
@@ -27,10 +27,10 @@
/// @file fake_vpd.H
/// @brief A tool to return fake (fixed) system VPD for testing, development
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef DOXYGEN
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
index 89ad19d7d..9b2a7a1af 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H
@@ -27,10 +27,10 @@
/// @file mss_pair.H
/// @brief Creates a pair class that has a constexpr constructor
///
-// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H
index 61a04a680..051aa214b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -28,9 +28,9 @@
/// @brief Miscellaneous number checking functions
///
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_NUM_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H
index b88b709db..012a93ce7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H
@@ -27,10 +27,10 @@
/// @file poll.H
/// @brief Poll a scom
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_POLL_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/swizzle.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/swizzle.H
index 6d2633531..260197a66 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/swizzle.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/swizzle.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,10 +27,10 @@
/// @file swizzle.H
/// @brief Swizzle bits
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: HB:FSP
#ifndef _MSS_SWIZZLE_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
index 18c2f419e..7e2f52ae9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.H
index ff25570ec..713a9505f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.H
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_ADR32S_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.H
index f6ea56402..cc82cd4d4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.H
@@ -26,7 +26,7 @@
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_DLL_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
index a5fa507bb..98e6a4479 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C
@@ -29,10 +29,10 @@
/// Workarounds are very deivce specific, so there is no attempt to generalize
/// this code in any way.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
index 2c9d3872d..40918277c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H
@@ -29,10 +29,10 @@
/// Workarounds are very deivce specific, so there is no attempt to generalize
/// this code in any way.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_DP16_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
index 0007acf80..3a1c039a4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.H
index 221e008a7..82ab4db42 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.H
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_MCA_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C
index 02e6ee099..eac039a06 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C
@@ -29,10 +29,10 @@
/// Workarounds are very deivce specific, so there is no attempt to generalize
/// this code in any way.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Steven Glancy <sglancy@usi.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H
index c10868907..e9d978be3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -29,10 +29,10 @@
/// Workarounds are very deivce specific, so there is no attempt to generalize
/// this code in any way.
///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
-// *HWP HWP Backup: Steven Glancy <sglancy@usi.ibm.com>
+// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_MCBIST_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
index 48fdb91d6..383dc5114 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
index 0c72fbeb2..6ff7fc925 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
@@ -32,7 +32,7 @@
// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_SEQ_H_
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.C
index 59791b9b6..e14ef0964 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.C
@@ -30,9 +30,9 @@
/// this code in any way.
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.H
index eb80bf52a..4350a8da7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/wr_vref_workarounds.H
@@ -30,9 +30,9 @@
/// this code in any way.
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#ifndef _MSS_WORKAROUNDS_WR_VREF_H_
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