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authorAlvin Wang <wangat@tw.ibm.com>2019-01-29 02:13:09 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-02-24 09:35:40 -0600
commit8f2fbd8180414a5dab93159b6c55974f569f358b (patch)
tree5ae6841d6c9a4bbd3664076358d286cb4b22e4db /src/import/chips/p9/procedures/hwp/memory/lib
parent361f7d64b58fe080aa47fe55df2604583700ed58 (diff)
downloadtalos-hostboot-8f2fbd8180414a5dab93159b6c55974f569f358b.tar.gz
talos-hostboot-8f2fbd8180414a5dab93159b6c55974f569f358b.zip
Reinstates exp_draminit_mc with change_addr_mux_sel fix
Change-Id: Ief62fadce588bf65e249ae771bd03ab31ed4bddf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71201 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71218 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H305
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H67
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H26
4 files changed, 108 insertions, 292 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
index 97e7fa229..75d15c1d1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C
@@ -72,7 +72,7 @@ constexpr uint64_t BIT_SPARE_7 = 15; // 7: SPARE
template<>
fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
{
- typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+ typedef portTraits<mss::mc_type::NIMBUS> TT;
uint32_t l_memcal_interval = 0;
uint32_t l_zqcal_interval = 0;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
index c2023ae27..1f5f06f43 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
@@ -25,7 +25,7 @@
///
/// @file port.H
-/// @brief Code to support ports (phy _ mc for certain operations)
+/// @brief Code to support ports
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
@@ -38,35 +38,41 @@
#include <fapi2.H>
-#include <p9_mc_scom_addresses.H>
-#include <p9_mc_scom_addresses_fld.H>
#include <lib/mss_attribute_accessors.H>
-#include <lib/utils/mss_nimbus_conversions.H>
#include <lib/shared/mss_const.H>
#include <generic/memory/lib/utils/scom.H>
-#include <lib/dimm/rank.H>
#include <generic/memory/lib/utils/c_str.H>
+#include <generic/memory/lib/utils/mc/gen_mss_port.H>
+#include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
+#include <lib/utils/mss_nimbus_conversions.H>
+#include <lib/dimm/rank.H>
#include <lib/mcbist/address.H>
namespace mss
{
-// I have a dream that port code can be shared among controllers. So, I drive the
-// engine from a set of traits. This might be folly. Allow me to dream. BRS
-
-template< fapi2::TargetType T >
-class portTraits;
-
-// Centaur port traits
+///
+/// @brief ATTR_MSS_MVPD_FWMS getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] uint32_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (G)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note Mark store records from MPVD Lx
+/// keyword
+///
template<>
-class portTraits<fapi2::TARGET_TYPE_MBA>
+inline fapi2::ReturnCode mvpd_fwms<mss::mc_type::NIMBUS>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+ uint32_t (&o_array)[mss::MARK_STORE_COUNT])
{
- public:
-};
+ return mvpd_fwms(i_target, &o_array[0]);
+}
-// Nimbus port traits
+///
+/// @class Traits and policy class for port code - specialization for Nimbus. The target of registers is TARGET_TYPE_MCA.
+///
template<>
-class portTraits<fapi2::TARGET_TYPE_MCA>
+class portTraits<mss::mc_type::NIMBUS>
{
public:
static constexpr uint64_t FARB5Q_REG = MCA_MBA_FARB5Q;
@@ -78,6 +84,7 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
static constexpr uint64_t CAL2Q_REG = MCA_MBA_CAL2Q;
static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q;
static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q;
+ static constexpr uint64_t FWMS_REG = MCA_FWMS0;
// Danger Will Robinson <wave robot arms> MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers
// which are different between PHYs. So if you're playing with this register, be sure to map rank numbers.
@@ -112,6 +119,9 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
CFG_DDR_RESETN = MCA_MBA_FARB5Q_CFG_DDR_RESETN,
CFG_CCS_ADDR_MUX_SEL = MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL,
+ FWMS0_MARK = MCA_FWMS0_MARK,
+ FWMS0_EXIT_1 = MCA_FWMS0_EXIT_1,
+
REFRESH_ENABLE = MCA_MBAREF0Q_CFG_REFRESH_ENABLE,
ECC_CHECK_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT,
@@ -231,6 +241,8 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW,
RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION,
RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY,
+ RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION,
+ RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN,
RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN,
DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY,
DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN,
@@ -271,43 +283,8 @@ class portTraits<fapi2::TARGET_TYPE_MCA>
};
};
-///
-/// @brief Read the read ECC Control register
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @param[out] o_buffer the buffer to write the register data into
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode read_recr_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_buffer )
-{
- FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) );
-
- FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) );
-
-fapi_try_exit:
- return fapi2::current_err;
-}
-
-///
-/// @brief Write to RECR register
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @param[in] i_buffer the buffer that holds the register data to write
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode write_recr_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_buffer )
-{
- FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) );
- FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) );
-fapi_try_exit:
- return fapi2::current_err;
-}
///
/// @brief Get the read pointer delay value from RECR
@@ -316,7 +293,7 @@ fapi_try_exit:
/// @param[in] i_data the data buffer containing the RECR register
/// @param[out] o_delay READ_POINTER_DLY value (in cycles)
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void get_read_pointer_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay )
{
i_data.template extractToRight<TT::RECR_READ_POINTER_DLY, TT::RECR_READ_POINTER_DLY_LEN>(o_delay);
@@ -331,7 +308,7 @@ void get_read_pointer_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_
/// @param[in,out] io_data the target data buffer
/// @param[in] i_delay READ_POINTER_DLY value (in cycles) to set
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void set_read_pointer_delay( fapi2::buffer<uint64_t>& io_data, const uint64_t i_delay )
{
FAPI_INF( "Set READ_POINTER_DLY to %d", i_delay);
@@ -339,35 +316,6 @@ void set_read_pointer_delay( fapi2::buffer<uint64_t>& io_data, const uint64_t i_
io_data.template insertFromRight<TT::RECR_READ_POINTER_DLY, TT::RECR_READ_POINTER_DLY_LEN>(i_delay);
}
-///
-/// @brief Get the tce correction enable value from RECR
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_data the data buffer containing the RECR register
-/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off)
-///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
-void get_tce_correction( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value )
-{
- o_value = i_data.template getBit<TT::RECR_TCE_CORRECTION>() ? mss::states::ON : mss::states::OFF;
-
- FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value );
-}
-
-///
-/// @brief Sets tce correction enable in buffer
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in,out] io_data the target data buffer
-/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set
-///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
-void set_tce_correction( fapi2::buffer<uint64_t>& io_data, const mss::states i_value )
-{
- FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value);
-
- io_data.template writeBit<TT::RECR_TCE_CORRECTION>(i_value);
-}
///
/// @brief Get the enable_ue_noise_window value from buffer
@@ -376,7 +324,7 @@ void set_tce_correction( fapi2::buffer<uint64_t>& io_data, const mss::states i_v
/// @param[in] i_data the data buffer containing the RECR register
/// @param[out] o_value ENABLE_UE_NOISE_WINDOW value (on or off)
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void get_enable_ue_noise_window( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value )
{
o_value = (i_data.template getBit<TT::RECR_ENABLE_UE_NOISE_WINDOW>()) ? mss::states::ON : mss::states::OFF;
@@ -391,7 +339,7 @@ void get_enable_ue_noise_window( const fapi2::buffer<uint64_t>& i_data, mss::sta
/// @param[in,out] io_data the target data buffer
/// @param[in] i_value ENABLE_UE_NOISE_WINDOW value (on or off) to set
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void set_enable_ue_noise_window( fapi2::buffer<uint64_t>& io_data, const mss::states i_value )
{
FAPI_INF( "Set ENABLE_UE_NOISE_WINDOW to %lu", i_value);
@@ -407,7 +355,7 @@ void set_enable_ue_noise_window( fapi2::buffer<uint64_t>& io_data, const mss::st
/// @param[in] i_target the target
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target<T>& i_target)
{
constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56;
@@ -415,7 +363,8 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target<T>& i_target)
fapi2::buffer<uint64_t> l_mnfg_buffer;
mss::states l_state = mss::OFF;
- FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target));
+ FAPI_TRY( mss::read_recr_register<mss::mc_type::NIMBUS>(i_target, l_data ), "%s: Failed read_recr_register",
+ mss::c_str(i_target));
mss::set_read_pointer_delay(l_data, mss::ON);
// Check for manufacturing disable dram repair flag to disable TCE correction
@@ -423,7 +372,8 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target<T>& i_target)
l_state = ( l_mnfg_buffer.getBit<MNFG_REPAIRS_DISABLED_ATTR>() ) ? mss::OFF : mss::ON;
mss::set_tce_correction(l_data, l_state);
- FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target));
+ FAPI_TRY( mss::write_recr_register<mss::mc_type::NIMBUS>(i_target, l_data), "%s: Failed write_recr_register",
+ mss::c_str(i_target));
fapi_try_exit:
return fapi2::current_err;
@@ -438,7 +388,7 @@ fapi_try_exit:
/// @param[out] o_delay the buffer to write the register data into
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode read_dsm0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_delay )
{
FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, o_delay) );
@@ -457,7 +407,7 @@ fapi_try_exit:
/// @param[in] i_delay the buffer that holds the register data to write
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode write_dsm0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_delay )
{
FAPI_INF( "Change Data State machine register to %d for %s", i_delay, mss::c_str(i_target) );
@@ -475,7 +425,7 @@ fapi_try_exit:
/// @param[in] i_data the data buffer containing the DSM0Q register
/// @param[out] o_delay WRDONE_DLY value (in cycles)
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void get_wrdone_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay )
{
i_data.template extractToRight<TT::DSM0Q_WRDONE_DLY, TT::DSM0Q_WRDONE_DLY_LEN>(o_delay);
@@ -490,7 +440,7 @@ void get_wrdone_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay
/// @param[in] i_delay WRDONE_DLY value (in cycles) to set
/// @param[in,out] io_data the target data buffer
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data )
{
FAPI_INF( "Set WRDONE_DLY to %d ", i_delay);
@@ -506,7 +456,7 @@ void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data
/// @param[in] i_delay WRDONE_DLY value (in cycles) to set
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode change_wrdone_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay )
{
fapi2::buffer<uint64_t> l_data;
@@ -530,7 +480,7 @@ fapi_try_exit:
/// @param[in] i_data the data buffer containing the DSM0Q register
/// @param[out] o_delay RDTAG_DLY value (in cycles)
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void get_rdtag_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay )
{
i_data.template extractToRight<TT::DSM0Q_RDTAG_DLY, TT::DSM0Q_RDTAG_DLY_LEN>(o_delay);
@@ -545,7 +495,7 @@ void get_rdtag_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay )
/// @param[in] i_delay RDTAG_DLY value (in cycles) to set
/// @param[in,out] io_data the target data buffer
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data )
{
FAPI_DBG( "Set RDTAG_DLY to %d ", i_delay);
@@ -562,7 +512,7 @@ void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data )
/// @param[in] i_delay new RDTAG_DLY value (in cycles) to set
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode change_rdtag_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay )
{
fapi2::buffer<uint64_t> l_data;
@@ -587,7 +537,7 @@ fapi_try_exit:
/// @param[out] o_time the buffer to read the register data into
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode read_farb0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_time )
{
FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_time) );
@@ -606,7 +556,7 @@ fapi_try_exit:
/// @param[in] i_delay the buffer containing the data to be written
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode write_farb0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_time )
{
FAPI_INF( "Change FARB0Q_REG to 0x%016lx for %s", uint64_t(i_time), mss::c_str(i_target) );
@@ -624,7 +574,7 @@ fapi_try_exit:
/// @param[in] i_data the data buffer containing the FARB0Q register
/// @param[out] o_time RCD_PROTECT_TIME value (in cycles)
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void get_rcd_protect_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_time )
{
i_data.template extractToRight<TT::FARB0Q_RCD_PROTECTION_TIME, TT::FARB0Q_RCD_PROTECTION_TIME_LEN>(o_time);
@@ -640,7 +590,7 @@ void get_rcd_protect_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_ti
/// @param[in] i_delay RCD Protect Time value (in cycles) to set
/// @param[in,out] io_data the target data buffer
///
-template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> >
+template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS> >
void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer<uint64_t>& io_data )
{
FAPI_DBG( "Set RCD_PROTECT_TIME to %d ", i_time);
@@ -656,7 +606,7 @@ void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer<uint64_t>& io_da
/// @param[in] i_time RCD Protect Time value (in cycles) to set
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode change_rcd_protect_time( const fapi2::Target<T>& i_target, const uint64_t i_time )
{
fapi2::buffer<uint64_t> l_data;
@@ -673,28 +623,6 @@ fapi_try_exit:
return fapi2::current_err;
}
-///
-/// @brief Change the state of the port_fail_disable bit
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-/// @note Disable Port Fail after recurring RCD errors.
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_port_fail_disable( const fapi2::Target<T>& i_target, states i_state )
-{
- fapi2::buffer<uint64_t> l_data;
-
- FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
- FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) );
- l_data.writeBit<TT::PORT_FAIL_DISABLE>(i_state);
- FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) );
-
-fapi_try_exit:
- return fapi2::current_err;
-}
///
/// @brief Change the state of the RCD recovery bit
@@ -704,7 +632,7 @@ fapi_try_exit:
/// @param[in] i_state the state
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode change_rcd_recovery_disable( const fapi2::Target<T>& i_target, states i_state )
{
fapi2::buffer<uint64_t> l_data;
@@ -726,7 +654,7 @@ fapi_try_exit:
/// @param[in] i_state the state
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode change_oe_always_on( const fapi2::Target<T>& i_target, states i_state )
{
fapi2::buffer<uint64_t> l_data;
@@ -740,50 +668,6 @@ fapi_try_exit:
return fapi2::current_err;
}
-///
-/// @brief Change the state of the addr_mux_sel bit
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target<T>& i_target, states i_state )
-{
- fapi2::buffer<uint64_t> l_data;
-
- FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
- FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) );
- l_data.writeBit<TT::CFG_CCS_ADDR_MUX_SEL>(i_state);
- FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
-
-fapi_try_exit:
- return fapi2::current_err;
-}
-
-
-///
-/// @brief Change the state of the MC Refresh enable bit
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @param[in] i_state the state
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode change_refresh_enable( const fapi2::Target<T>& i_target, states i_state )
-{
- fapi2::buffer<uint64_t> l_data;
-
- FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target));
- FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) );
- l_data.writeBit<TT::REFRESH_ENABLE>(i_state);
- FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) );
-
-fapi_try_exit:
- return fapi2::current_err;
-}
///
/// @brief Enable the MC Periodic calibration functionality
@@ -792,7 +676,7 @@ fapi_try_exit:
/// @param[in] i_target the target
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<T>& i_target );
///
@@ -803,45 +687,6 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<T>& i_target );
template<>
fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
-///
-/// @brief Enable Read ECC checking
-/// @tparam T the fapi2 target type of the target
-/// @tparam TT the class traits for the port
-/// @param[in] i_target the target
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target )
-{
- fapi2::buffer<uint64_t> l_data;
-
- uint8_t l_sim = 0;
- FAPI_TRY( mss::is_simulation(l_sim) );
-
- FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target));
-
- FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) );
- l_data.clearBit<TT::ECC_CHECK_DISABLE>();
- l_data.clearBit<TT::ECC_CORRECT_DISABLE>();
-
- // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything)
- // so we can't run with address checking. Disable address checking in sim.
- l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1);
-
- // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented
- // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but
- // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15
- // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC
- l_data.insertFromRight<MCA_RECR_MBSECCQ_DATA_INVERSION, MCA_RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11);
-
- // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE
- // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus.
-
- FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) );
-
-fapi_try_exit:
- return fapi2::current_err;
-}
//
// We expect to come in to draminit with the following setup:
@@ -860,7 +705,7 @@ fapi_try_exit:
// This is in this header as it's hoped to be able to be shared. Seems to make more
// Might make more sense in p9_mss_draminit.C ... BRS
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target<T>& i_target )
{
fapi2::buffer<uint64_t> l_data;
@@ -889,7 +734,7 @@ fapi_try_exit:
/// @return FAPI2_RC_SUCCESS if and only if ok
/// @note this might need a port id added for Centaur/MBA controllers
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode drive_mem_clks( const fapi2::Target<T>& i_target, const uint64_t i_pclk, const uint64_t i_nclk )
{
fapi2::buffer<uint64_t> l_data;
@@ -918,7 +763,7 @@ fapi_try_exit:
/// @return FAPI2_RC_SUCCESS if and only if ok
/// @note this might need a port id added for Centaur/MBA controllers
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode ddr_resetn( const fapi2::Target<T>& i_target, const bool i_state )
{
fapi2::buffer<uint64_t> l_data;
@@ -951,43 +796,13 @@ fapi_try_exit:
}
///
-/// @brief Apply mark store bits from module VPD
-/// @tparam T, the fapi2 target type of the target
-/// @tparam TT, the class traits for the port
-/// @param[in] i_target A target representing a port
-/// @return FAPI2_RC_SUCCESS if and only if ok
-///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
-fapi2::ReturnCode apply_mark_store( const fapi2::Target<T>& i_target )
-{
- FAPI_INF("Enable marks from MVPD");
-
- uint32_t l_fwms[MARK_STORE_COUNT];
-
- FAPI_TRY( mss::mvpd_fwms(i_target, &(l_fwms[0])) );
-
- for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark)
- {
- if (l_fwms[l_mark] != 0)
- {
- fapi2::buffer<uint64_t> l_fwms_data;
- l_fwms_data.insertFromRight < MCA_FWMS0_MARK, MCA_FWMS0_EXIT_1 - MCA_FWMS0_MARK + 1 > (l_fwms[l_mark]);
- FAPI_TRY( mss::putScom(i_target, MCA_FWMS0 + l_mark, l_fwms_data) );
- }
- }
-
-fapi_try_exit:
- return fapi2::current_err;
-}
-
-///
/// @brief Reset the ZCAL config register.
/// @warning This maps PHY rank numbers per target
/// @tparam T, the fapi2 target type of the target
/// @param[in] i_target A target representing a port
/// @return FAPI2_RC_SUCCESS if and only if ok
///
-template< fapi2::TargetType T, typename TT = portTraits<T> >
+template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS> >
fapi2::ReturnCode reset_zqcal_config( const fapi2::Target<T>& i_target )
{
fapi2::buffer<uint64_t> l_phy_zqcal_config;
@@ -1016,7 +831,7 @@ fapi_try_exit:
///
inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state)
{
- typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+ typedef portTraits<mss::mc_type::NIMBUS> TT;
fapi2::buffer<uint64_t> l_data;
@@ -1064,7 +879,7 @@ fapi_try_exit:
///
inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state)
{
- typedef portTraits<fapi2::TARGET_TYPE_MCA> TT;
+ typedef portTraits<mss::mc_type::NIMBUS> TT;
fapi2::buffer<uint64_t> l_data;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index e27f82f69..d5840df40 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -14330,28 +14330,6 @@ fapi_try_exit:
}
///
-/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter
-/// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note Memory power control settings programmed during IPL Used by OCC when exiting
-/// idle power-save
-/// mode
-///
-inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value)
-{
-
- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
- o_value) );
- return fapi2::current_err;
-
-fapi_try_exit:
- FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)",
- uint64_t(fapi2::current_err));
- return fapi2::current_err;
-}
-
-///
/// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
@@ -21478,6 +21456,51 @@ fapi_try_exit:
}
+///
+/// @brief ATTR_MEM_MRW_IS_PLANAR getter
+/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note Indicates if the DIMM connected to this controller are in a planar
+/// configuration
+///
+inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+ uint8_t& o_value)
+{
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) );
+ return fapi2::current_err;
+
+fapi_try_exit:
+ FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx",
+ uint64_t(fapi2::current_err));
+ return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note Memory power control settings programmed during IPL Used by OCC when exiting
+/// idle power-save
+/// mode
+///
+inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value)
+{
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ o_value) );
+ return fapi2::current_err;
+
+fapi_try_exit:
+ FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)",
+ uint64_t(fapi2::current_err));
+ return fapi2::current_err;
+}
+
+
}
#endif
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
index 7c89b99a6..510cc1a19 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
@@ -43,6 +43,8 @@
namespace mss
{
+constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::NIMBUS;
+
enum sizes
{
PORTS_PER_MCS = 2,
@@ -74,7 +76,6 @@ enum sizes
NUM_LRDIMM_TRAINING_PATTERNS = 5, ///< Used for ATTR_MSS_LRDIMM_TRAINING_PATTERN
- MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array
BAD_DQ_BYTE_COUNT = 10, ///< Elements in a BAD_DQ_BITMAP attribute array
ROW_REPAIR_BYTE_COUNT = 4, ///< Elements in a ROW_REPAIR_DATA attribute array.
@@ -216,29 +217,6 @@ enum ffdc_function_codes
MREP_CALL_OUT = 131,
};
-enum states
-{
- LOW = 0,
- HIGH = 1,
- START = 1,
- STOP = 0,
- START_N = 0,
- STOP_N = 1,
- ON = 1,
- OFF = 0,
- ON_N = 0,
- OFF_N = 1,
- YES = 1,
- NO = 0,
- YES_N = 0,
- NO_N = 1,
- // Uses "_" in the name for INVALID as INVALID is defined as a macro in the
- // FSP code. If we just use INVALID as an enum name, then the preprocessor
- // compile phase changes it to be the macro.
- _INVALID_ = 0xFF,
- NO_CHIP_SELECT_ACTIVE = 0xFF,
-};
-
// Static consts describing the bits used in the cal_step_enable attribute
// These are bit positions. 0 is the left most bit.
enum cal_steps : uint64_t
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