Move MSS Rosetta map from lab to f/w library, add API

Change-Id: I3f0f9f449f2cf8db6bc99bf4bdfd9212950d65d2
Original-Change-Id: I85cf0991ed0c12c11abf980015b5e1a79cc2c450
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42116
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52084
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 803 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
new file mode 100644
index 000000000..b1c8560e5
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
@@ -0,0 +1,386 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+
+///
+/// @file rosetta_map.C
+/// @brief Mapping tables for memory controller pin names to PHY instance names
+/// @note: this file is automatically generated by gen_rosetta_map.pl
+///        from input file chips/p9/procedures/hwp/memory/lib/rosetta_map/src_data/Monza_DDR_pin_xref.csv
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#include <rosetta_map.H>
+
+namespace mss
+{
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, DQ>::C4_TO_PHY =
+{
+    {   {2, 6}, {2, 4}, {2, 5}, {2, 7}, {2, 2}, {2, 0}, {2, 1}, {2, 3}, {4, 6}, {4, 4}, {4, 5}, {4, 7}, {4, 0}, {4, 2}, {4, 1}, {4, 3},
+        {3, 4}, {3, 6}, {3, 7}, {3, 5}, {3, 2}, {3, 0}, {3, 1}, {3, 3}, {3, 9}, {3, 11}, {3, 10}, {3, 8}, {3, 13}, {3, 15}, {3, 12}, {3, 14},
+        {1, 2}, {1, 0}, {1, 3}, {1, 1}, {1, 5}, {1, 4}, {1, 6}, {1, 7}, {0, 5}, {0, 7}, {0, 4}, {0, 6}, {0, 3}, {0, 1}, {0, 2}, {0, 0},
+        {1, 14}, {1, 12}, {1, 15}, {1, 13}, {1, 10}, {1, 8}, {1, 9}, {1, 11}, {0, 13}, {0, 15}, {0, 12}, {0, 14}, {0, 11}, {0, 9}, {0, 10}, {0, 8},
+        {2, 14}, {2, 13}, {2, 15}, {2, 12}, {2, 10}, {2, 8}, {2, 11}, {2, 9}
+    },
+    {   {3, 0}, {3, 1}, {3, 3}, {3, 2}, {3, 4}, {3, 5}, {3, 6}, {3, 7}, {4, 5}, {4, 7}, {4, 6}, {4, 4}, {4, 1}, {4, 2}, {4, 0}, {4, 3},
+        {3, 10}, {3, 11}, {3, 9}, {3, 8}, {3, 13}, {3, 15}, {3, 12}, {3, 14}, {2, 6}, {2, 4}, {2, 7}, {2, 5}, {2, 1}, {2, 0}, {2, 3}, {2, 2},
+        {1, 6}, {1, 4}, {1, 7}, {1, 5}, {1, 0}, {1, 2}, {1, 3}, {1, 1}, {1, 11}, {1, 9}, {1, 8}, {1, 10}, {1, 15}, {1, 13}, {1, 14}, {1, 12},
+        {0, 15}, {0, 13}, {0, 12}, {0, 14}, {0, 9}, {0, 11}, {0, 8}, {0, 10}, {0, 1}, {0, 3}, {0, 2}, {0, 0}, {0, 7}, {0, 5}, {0, 4}, {0, 6},
+        {2, 15}, {2, 14}, {2, 13}, {2, 12}, {2, 9}, {2, 10}, {2, 8}, {2, 11}
+    },
+    {   {4, 4}, {4, 6}, {4, 7}, {4, 5}, {4, 0}, {4, 2}, {4, 3}, {4, 1}, {3, 10}, {3, 8}, {3, 11}, {3, 9}, {3, 13}, {3, 15}, {3, 14}, {3, 12},
+        {3, 4}, {3, 6}, {3, 5}, {3, 7}, {3, 0}, {3, 2}, {3, 1}, {3, 3}, {2, 3}, {2, 1}, {2, 2}, {2, 0}, {2, 5}, {2, 7}, {2, 6}, {2, 4},
+        {0, 1}, {0, 3}, {0, 0}, {0, 2}, {0, 5}, {0, 7}, {0, 4}, {0, 6}, {2, 15}, {2, 13}, {2, 12}, {2, 14}, {2, 10}, {2, 8}, {2, 11}, {2, 9},
+        {1, 15}, {1, 13}, {1, 12}, {1, 14}, {1, 11}, {1, 8}, {1, 9}, {1, 10}, {0, 11}, {0, 9}, {0, 8}, {0, 10}, {0, 13}, {0, 15}, {0, 12}, {0, 14},
+        {1, 0}, {1, 2}, {1, 1}, {1, 3}, {1, 4}, {1, 6}, {1, 5}, {1, 7}
+    },
+    {   {4, 0}, {4, 2}, {4, 3}, {4, 1}, {4, 4}, {4, 6}, {4, 5}, {4, 7}, {2, 0}, {2, 2}, {2, 1}, {2, 3}, {2, 4}, {2, 6}, {2, 7}, {2, 5},
+        {3, 9}, {3, 11}, {3, 8}, {3, 10}, {3, 15}, {3, 13}, {3, 14}, {3, 12}, {2, 11}, {2, 9}, {2, 10}, {2, 8}, {2, 13}, {2, 15}, {2, 14}, {2, 12},
+        {0, 8}, {0, 10}, {0, 9}, {0, 11}, {0, 12}, {0, 14}, {0, 13}, {0, 15}, {0, 5}, {0, 7}, {0, 6}, {0, 4}, {0, 1}, {0, 3}, {0, 0}, {0, 2},
+        {1, 10}, {1, 8}, {1, 11}, {1, 9}, {1, 12}, {1, 14}, {1, 15}, {1, 13}, {1, 4}, {1, 6}, {1, 5}, {1, 7}, {1, 0}, {1, 2}, {1, 1}, {1, 3},
+        {3, 2}, {3, 0}, {3, 1}, {3, 3}, {3, 6}, {3, 4}, {3, 7}, {3, 5}
+    },
+    {   {3, 13}, {3, 15}, {3, 14}, {3, 12}, {3, 9}, {3, 11}, {3, 8}, {3, 10}, {2, 4}, {2, 6}, {2, 7}, {2, 5}, {2, 2}, {2, 0}, {2, 3}, {2, 1},
+        {4, 4}, {4, 6}, {4, 7}, {4, 5}, {4, 0}, {4, 2}, {4, 3}, {4, 1}, {3, 2}, {3, 0}, {3, 3}, {3, 1}, {3, 6}, {3, 4}, {3, 7}, {3, 5},
+        {0, 4}, {0, 6}, {0, 7}, {0, 5}, {0, 0}, {0, 2}, {0, 3}, {0, 1}, {0, 14}, {0, 12}, {0, 15}, {0, 13}, {0, 10}, {0, 8}, {0, 11}, {0, 9},
+        {2, 12}, {2, 14}, {2, 15}, {2, 13}, {2, 10}, {2, 8}, {2, 11}, {2, 9}, {1, 7}, {1, 4}, {1, 5}, {1, 6}, {1, 1}, {1, 0}, {1, 3}, {1, 2},
+        {1, 15}, {1, 13}, {1, 12}, {1, 14}, {1, 9}, {1, 11}, {1, 8}, {1, 10}
+    },
+    {   {3, 3}, {3, 1}, {3, 2}, {3, 0}, {3, 7}, {3, 5}, {3, 4}, {3, 6}, {4, 1}, {4, 3}, {4, 0}, {4, 2}, {4, 7}, {4, 5}, {4, 6}, {4, 4},
+        {3, 9}, {3, 11}, {3, 10}, {3, 8}, {3, 15}, {3, 13}, {3, 12}, {3, 14}, {2, 7}, {2, 5}, {2, 4}, {2, 6}, {2, 1}, {2, 3}, {2, 2}, {2, 0},
+        {1, 14}, {1, 12}, {1, 13}, {1, 15}, {1, 8}, {1, 10}, {1, 9}, {1, 11}, {0, 4}, {0, 6}, {0, 7}, {0, 5}, {0, 0}, {0, 2}, {0, 3}, {0, 1},
+        {0, 14}, {0, 12}, {0, 15}, {0, 13}, {0, 8}, {0, 10}, {0, 9}, {0, 11}, {1, 2}, {1, 3}, {1, 0}, {1, 1}, {1, 4}, {1, 7}, {1, 6}, {1, 5},
+        {2, 11}, {2, 9}, {2, 10}, {2, 8}, {2, 13}, {2, 15}, {2, 12}, {2, 14}
+    },
+    {   {4, 2}, {4, 0}, {4, 3}, {4, 1}, {4, 6}, {4, 4}, {4, 5}, {4, 7}, {3, 6}, {3, 4}, {3, 7}, {3, 5}, {3, 0}, {3, 2}, {3, 3}, {3, 1},
+        {3, 9}, {3, 11}, {3, 8}, {3, 10}, {3, 15}, {3, 13}, {3, 14}, {3, 12}, {2, 4}, {2, 6}, {2, 7}, {2, 5}, {2, 0}, {2, 2}, {2, 1}, {2, 3},
+        {1, 2}, {1, 0}, {1, 3}, {1, 1}, {1, 5}, {1, 4}, {1, 6}, {1, 7}, {0, 5}, {0, 7}, {0, 4}, {0, 6}, {0, 3}, {0, 1}, {0, 2}, {0, 0},
+        {1, 14}, {1, 12}, {1, 15}, {1, 13}, {1, 10}, {1, 8}, {1, 9}, {1, 11}, {0, 13}, {0, 15}, {0, 14}, {0, 12}, {0, 11}, {0, 9}, {0, 10}, {0, 8},
+        {2, 8}, {2, 9}, {2, 11}, {2, 10}, {2, 13}, {2, 15}, {2, 12}, {2, 14}
+    },
+    {   {2, 4}, {2, 6}, {2, 7}, {2, 5}, {2, 0}, {2, 2}, {2, 1}, {2, 3}, {3, 1}, {3, 3}, {3, 0}, {3, 2}, {3, 5}, {3, 7}, {3, 6}, {3, 4},
+        {4, 2}, {4, 0}, {4, 3}, {4, 1}, {4, 4}, {4, 6}, {4, 5}, {4, 7}, {2, 13}, {2, 15}, {2, 14}, {2, 12}, {2, 8}, {2, 11}, {2, 10}, {2, 9},
+        {1, 5}, {1, 7}, {1, 6}, {1, 4}, {1, 0}, {1, 2}, {1, 1}, {1, 3}, {1, 13}, {1, 15}, {1, 14}, {1, 12}, {1, 11}, {1, 9}, {1, 10}, {1, 8},
+        {0, 10}, {0, 8}, {0, 9}, {0, 11}, {0, 12}, {0, 14}, {0, 13}, {0, 15}, {0, 1}, {0, 3}, {0, 0}, {0, 2}, {0, 7}, {0, 5}, {0, 4}, {0, 6},
+        {3, 11}, {3, 9}, {3, 10}, {3, 8}, {3, 13}, {3, 15}, {3, 14}, {3, 12}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, DQS>::C4_TO_PHY =
+{
+    {   {2, 18}, {4, 18}, {3, 18}, {3, 20}, {1, 16}, {0, 18}, {1, 22}, {0, 22}, {2, 22}, {2, 16}, {4, 16}, {3, 16}, {3, 22}, {1, 18}, {0, 16}, {1, 20},
+        {0, 20}, {2, 20}
+    },
+    {   {3, 16}, {4, 18}, {3, 20}, {2, 18}, {1, 18}, {1, 20}, {0, 22}, {0, 16}, {2, 22}, {3, 18}, {4, 16}, {3, 22}, {2, 16}, {1, 16}, {1, 22}, {0, 20},
+        {0, 18}, {2, 20}
+    },
+    {   {4, 18}, {3, 20}, {3, 18}, {2, 16}, {0, 16}, {2, 22}, {1, 22}, {0, 20}, {1, 16}, {4, 16}, {3, 22}, {3, 16}, {2, 18}, {0, 18}, {2, 20}, {1, 20},
+        {0, 22}, {1, 18}
+    },
+    {   {4, 16}, {2, 16}, {3, 20}, {2, 20}, {0, 20}, {0, 18}, {1, 20}, {1, 18}, {3, 16}, {4, 18}, {2, 18}, {3, 22}, {2, 22}, {0, 22}, {0, 16}, {1, 22},
+        {1, 16}, {3, 18}
+    },
+    {   {3, 22}, {2, 18}, {4, 18}, {3, 16}, {0, 18}, {0, 22}, {2, 22}, {1, 18}, {1, 22}, {3, 20}, {2, 16}, {4, 16}, {3, 18}, {0, 16}, {0, 20}, {2, 20},
+        {1, 16}, {1, 20}
+    },
+    {   {3, 16}, {4, 16}, {3, 20}, {2, 18}, {1, 22}, {0, 18}, {0, 22}, {1, 16}, {2, 20}, {3, 18}, {4, 18}, {3, 22}, {2, 16}, {1, 20}, {0, 16}, {0, 20},
+        {1, 18}, {2, 22}
+    },
+    {   {4, 16}, {3, 18}, {3, 20}, {2, 18}, {1, 16}, {0, 18}, {1, 22}, {0, 22}, {2, 20}, {4, 18}, {3, 16}, {3, 22}, {2, 16}, {1, 18}, {0, 16}, {1, 20},
+        {0, 20}, {2, 22}
+    },
+    {   {2, 18}, {3, 16}, {4, 16}, {2, 22}, {1, 18}, {1, 22}, {0, 20}, {0, 16}, {3, 20}, {2, 16}, {3, 18}, {4, 18}, {2, 20}, {1, 16}, {1, 20}, {0, 22},
+        {0, 18}, {3, 22}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, ADDRESS>::C4_TO_PHY =
+{
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    },
+    {   {0, 8}, {2, 5}, {1, 10}, {2, 4}, {2, 6}, {2, 3}, {2, 9}, {2, 7}, {2, 2}, {2, 8}, {0, 5}, {3, 1}, {2, 11}, {1, 0}, {0, 1}, {0, 11},
+        {2, 1}, {1, 4}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, CLOCK>::C4_TO_PHY =
+{
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    },
+    {   {1, 3}, {1, 2}, {1, 7}, {1, 6}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, WE>::C4_TO_PHY =
+{
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    },
+    {   {0, 1}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, RAS>::C4_TO_PHY =
+{
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    },
+    {   {2, 1}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, CAS>::C4_TO_PHY =
+{
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    },
+    {   {0, 11}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, CS>::C4_TO_PHY =
+{
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    },
+    {   {0, 0}, {1, 1}, {2, 0}, {1, 9}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, CKE>::C4_TO_PHY =
+{
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    },
+    {   {3, 3}, {2, 10}, {3, 6}, {3, 4}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, ODT>::C4_TO_PHY =
+{
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    },
+    {   {0, 10}, {0, 6}, {0, 9}, {0, 2}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, BA>::C4_TO_PHY =
+{
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    },
+    {   {0, 7}, {0, 4}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, BG>::C4_TO_PHY =
+{
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    },
+    {   {3, 2}, {3, 5}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, CID>::C4_TO_PHY =
+{
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    },
+    {   {0, 3}, {1, 5}, {1, 8}
+    }
+};
+
+// Each pin type has a table of vector<vector<pair>>, indexed by [port][MC c4bit]-->{block, lane}
+const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, ACTN>::C4_TO_PHY =
+{
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    },
+    {   {3, 0}
+    }
+};
+
+} // ns mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
new file mode 100644
index 000000000..6e6771f73
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
@@ -0,0 +1,417 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file rosetta_map.H
+/// @brief Mapping functions for module C4 pin names to PHY instance names
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_ROSETTA_MAP_H_
+#define _MSS_ROSETTA_MAP_H_
+
+#include <vector>
+#include <algorithm>
+#include <fapi2.H>
+
+#include <lib/mss_attribute_accessors.H>
+#include <lib/shared/mss_const.H>
+
+namespace mss
+{
+
+///
+/// @brief Types of signals/pins mapped by the rosetta_map
+///
+enum rosetta_type
+{
+    DQ,
+    DQS,
+    ADDRESS,
+    CLOCK,
+    WE,
+    RAS,
+    CAS,
+    CS,
+    CKE,
+    ODT,
+    BA,
+    BG,
+    CID,
+    ACTN
+};
+
+///
+/// @brief c_str specialization for rosetta_type
+/// @param[in] i_input - input you want the const char * for
+/// @return const char * representation of given rosetta_type
+///
+inline const char* c_str( const rosetta_type& i_input )
+{
+    switch (i_input)
+    {
+        case DQ:
+            sprintf(c_str_storage, "DQ");
+            break;
+
+        case DQS:
+            sprintf(c_str_storage, "DQS");
+            break;
+
+        case ADDRESS:
+            sprintf(c_str_storage, "ADDRESS");
+            break;
+
+        case CLOCK:
+            sprintf(c_str_storage, "CLOCK");
+            break;
+
+        case WE:
+            sprintf(c_str_storage, "WE");
+            break;
+
+        case RAS:
+            sprintf(c_str_storage, "RAS");
+            break;
+
+        case CAS:
+            sprintf(c_str_storage, "CAS");
+            break;
+
+        case CS:
+            sprintf(c_str_storage, "CS");
+            break;
+
+        case CKE:
+            sprintf(c_str_storage, "CKE");
+            break;
+
+        case ODT:
+            sprintf(c_str_storage, "ODT");
+            break;
+
+        case BA:
+            sprintf(c_str_storage, "BA");
+            break;
+
+        case BG:
+            sprintf(c_str_storage, "BG");
+            break;
+
+        case CID:
+            sprintf(c_str_storage, "CID");
+            break;
+
+        case ACTN:
+            sprintf(c_str_storage, "ACTN");
+            break;
+
+        default:
+            sprintf(c_str_storage, "ERROR");
+            break;
+    }
+
+    return c_str_storage;
+}
+
+namespace rosetta_map
+{
+
+// PhyMap is an alias for the mapping table for each pin type mapped in the rosetta_map
+using PhyMap = std::vector<std::vector<std::pair<uint64_t, uint64_t>>>;
+
+} // close namespace rosetta_map
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the module C4 to PHY pin mapping
+/// @tparam T fapi2::TargetType representing the PHY
+/// @tparam R rosetta_type enumeration of signal/pin to map
+///
+template< fapi2::TargetType T, rosetta_type R >
+class rosettaTraits;
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for DQ
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQ>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for DQS
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQS>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for ADDRESS
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, ADDRESS>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for CLOCK
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, CLOCK>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for WE
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, WE>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for RAS
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, RAS>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for CAS
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, CAS>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for CS
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, CS>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for CKE
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, CKE>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for ODT
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, ODT>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for BA
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, BA>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for BG
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, BG>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for CID
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, CID>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+///
+/// @class rosettaTraits
+/// @brief a collection of traits associated with the Nimbus module c4 pin to PHY instance mapping for ACTN
+///
+template<>
+class rosettaTraits<fapi2::TARGET_TYPE_MCA, ACTN>
+{
+    public:
+        // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
+        static const rosetta_map::PhyMap C4_TO_PHY;
+};
+
+namespace rosetta_map
+{
+
+///
+/// @brief Given a module C4 pin index, return the PHY DP16 instance and lane
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rosettaTraits<T, R>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_c4_pin the index of the module C4 pin
+/// @param[out] o_dp the DP instance
+/// @param[out] o_lane the lane index
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T, typename TT = rosettaTraits<T, R> >
+fapi2::ReturnCode c4_to_phy( const fapi2::Target<T>& i_target,
+                             const uint64_t i_c4_pin,
+                             uint64_t& o_dp,
+                             uint64_t& o_lane )
+{
+    const auto l_pos = mss::pos(i_target);
+    const auto& l_mapping = TT::C4_TO_PHY[l_pos];
+    char l_str_buffer[fapi2::MAX_ECMD_STRING_LEN] = {};
+
+    // Make a copy of c_str(R) so it doesn't get overwritten by mss::c_str(i_target)
+    strcpy(l_str_buffer, c_str(R));
+
+    FAPI_ASSERT(i_c4_pin < l_mapping.size(),
+                fapi2::MSS_C4_PIN_OUT_OF_RANGE()
+                .set_MCA_TARGET(i_target)
+                .set_TYPE(R)
+                .set_INDEX(i_c4_pin),
+                "%s Module C4 pin type %s, index %d is beyond maximum value %d", mss::c_str(i_target), l_str_buffer, i_c4_pin,
+                (l_mapping.size() - 1) );
+
+    o_dp   = l_mapping[i_c4_pin].first;
+    o_lane = l_mapping[i_c4_pin].second;
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Given a PHY DP16 instance and lane, return the corresponding module C4 pin index
+/// @tparam R rosetta_type enumeration of signal/pin to map
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to rosettaTraits<T, R>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_dp the DP instance
+/// @param[in] i_lane the lane index
+/// @param[out] o_c4_pin the index of the module C4 pin
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+template< rosetta_type R, fapi2::TargetType T, typename TT = rosettaTraits<T, R> >
+fapi2::ReturnCode phy_to_c4( const fapi2::Target<T>& i_target,
+                             const uint64_t i_dp,
+                             const uint64_t i_lane,
+                             uint64_t& o_c4_pin )
+{
+    const auto l_pos = mss::pos(i_target);
+    const auto& l_mapping = TT::C4_TO_PHY[l_pos];
+    char l_str_buffer[fapi2::MAX_ECMD_STRING_LEN] = {};
+
+    // Make a copy of c_str(R) so it doesn't get overwritten by mss::c_str(i_target)
+    strcpy(l_str_buffer, c_str(R));
+
+    const auto l_it = std::find(l_mapping.begin(), l_mapping.end(), std::make_pair(i_dp, i_lane));
+
+    FAPI_ASSERT(l_it != l_mapping.end(),
+                fapi2::MSS_NO_C4_PIN_MAPPING()
+                .set_MCA_TARGET(i_target)
+                .set_TYPE(R)
+                .set_DP(i_dp)
+                .set_LANE(i_lane),
+                "%s No module C4 pin mapping found for type %s, DP %d, lane %d", mss::c_str(i_target), l_str_buffer, i_dp, i_lane );
+
+    o_c4_pin = l_it - l_mapping.begin();
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+} // close namespace rosetta_map
+} // close namespace mss
+
+#endif