Rename access_delay_regs API perspective MC to C4 and add real MC perspective

Change-Id: Icd1a30f3eaab67f609928dc30fadf40d1535c84f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44519
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52086
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 23 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
index e88b9b413..39ef0439e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.C
@@ -383,4 +383,21 @@ const rosetta_map::PhyMap rosettaTraits<fapi2::TARGET_TYPE_MCA, ACTN>::C4_TO_PHY
     }
 };
 
+// Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+const std::vector<std::pair<uint64_t, uint64_t>> rosettaTraits<fapi2::TARGET_TYPE_MCA, DQ>::MC_TO_PHY =
+{
+    {0, 0}, {0, 1}, {0, 2}, {0, 3}, {0, 4}, {0, 5}, {0, 6}, {0, 7}, {0, 8}, {0, 9}, {0, 10}, {0, 11}, {0, 12}, {0, 13}, {0, 14}, {0, 15},
+    {1, 0}, {1, 1}, {1, 2}, {1, 3}, {1, 4}, {1, 5}, {1, 6}, {1, 7}, {1, 8}, {1, 9}, {1, 10}, {1, 11}, {1, 12}, {1, 13}, {1, 14}, {1, 15},
+    {2, 0}, {2, 1}, {2, 2}, {2, 3}, {2, 4}, {2, 5}, {2, 6}, {2, 7}, {2, 8}, {2, 9}, {2, 10}, {2, 11}, {2, 12}, {2, 13}, {2, 14}, {2, 15},
+    {3, 0}, {3, 1}, {3, 2}, {3, 3}, {3, 4}, {3, 5}, {3, 6}, {3, 7}, {3, 8}, {3, 9}, {3, 10}, {3, 11}, {3, 12}, {3, 13}, {3, 14}, {3, 15},
+    {4, 0}, {4, 1}, {4, 2}, {4, 3}, {4, 4}, {4, 5}, {4, 6}, {4, 7},
+};
+
+// Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+const std::vector<std::pair<uint64_t, uint64_t>> rosettaTraits<fapi2::TARGET_TYPE_MCA, DQS>::MC_TO_PHY =
+{
+    {0, 16}, {0, 20}, {1, 16}, {1, 20}, {2, 16}, {2, 20}, {3, 16}, {3, 20}, {4, 16}, {0, 18}, {0, 22}, {1, 18}, {1, 22}, {2, 18}, {2, 22}, {3, 18},
+    {3, 22}, {4, 18},
+};
+
 } // ns mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
index 6e6771f73..329bfa4d2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H
@@ -167,6 +167,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQ>
     public:
         // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
         static const rosetta_map::PhyMap C4_TO_PHY;
+        // Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+        static const std::vector<std::pair<uint64_t, uint64_t>> MC_TO_PHY;
 };
 
 ///
@@ -179,6 +181,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, DQS>
     public:
         // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
         static const rosetta_map::PhyMap C4_TO_PHY;
+        // Map from MC index to PHY pin. Not a PhyMap because it's the same for every port
+        static const std::vector<std::pair<uint64_t, uint64_t>> MC_TO_PHY;
 };
 
 ///
@@ -191,6 +195,8 @@ class rosettaTraits<fapi2::TARGET_TYPE_MCA, ADDRESS>
     public:
         // Each pin type has a table of vector<vector<pair>>, indexed by [port][c4bit]-->{block, lane}
         static const rosetta_map::PhyMap C4_TO_PHY;
+        // Constexpr defines how many pins there are on an ADR instance
+        static constexpr uint64_t PINS_PER_ADR = 12;
 };
 
 ///