Added mss::get/putScom

Change-Id: I1bb2ae73d4c90c771a285b292b04b566e302fafc
Original-Change-Id: Ib6571e6e9e374c6d8995235e2553bce149b0113b
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22988
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Christian Geddes <crgeddes@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22760
Tested-by: FSP CI Jenkins
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 46 insertions, 45 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index cccb0b3e1..b8a9917cf 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -67,7 +67,7 @@ fapi2::ReturnCode scom_blastah( const fapi2::Target<T>& i_target, const std::vec
 
     for (auto a : i_addrs)
     {
-        FAPI_TRY( fapi2::putScom(i_target, a, i_data) );
+        FAPI_TRY( mss::putScom(i_target, a, i_data) );
         ++count;
     }
 
@@ -93,7 +93,7 @@ fapi2::ReturnCode scom_blastah( const std::vector<fapi2::Target<T> >& i_targets,
 
     for (auto t : i_targets)
     {
-        FAPI_TRY( fapi2::putScom(t, i_addr, i_data) );
+        FAPI_TRY( mss::putScom(t, i_addr, i_data) );
         ++count;
     }
 
@@ -145,9 +145,9 @@ fapi2::ReturnCode change_resetn( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targ
     {
         FAPI_DBG("Change reset to %s PHY: %s", (i_state == HIGH ? "high" : "low"), mss::c_str(p));
 
-        FAPI_TRY( fapi2::getScom(p, MCA_MBA_CAL0Q, l_data) );
+        FAPI_TRY( mss::getScom(p, MCA_MBA_CAL0Q, l_data) );
         i_state == HIGH ? l_data.setBit<MCA_MBA_CAL0Q_RESET_RECOVER>() : l_data.clearBit<MCA_MBA_CAL0Q_RESET_RECOVER>();
-        FAPI_TRY( fapi2::putScom(p, MCA_MBA_CAL0Q, l_data) );
+        FAPI_TRY( mss::putScom(p, MCA_MBA_CAL0Q, l_data) );
     }
 
 fapi_try_exit:
@@ -221,7 +221,7 @@ fapi2::ReturnCode change_force_mclk_low (const fapi2::Target<fapi2::TARGET_TYPE_
     // Might as well do this for all the ports while we're here.
     for (auto p : i_target.getChildren<TARGET_TYPE_MCA>())
     {
-        FAPI_TRY(fapi2::getScom( p, MCA_MBA_FARB5Q, l_data));
+        FAPI_TRY(mss::getScom( p, MCA_MBA_FARB5Q, l_data));
 
         if (i_state == mss::HIGH)
         {
@@ -232,7 +232,7 @@ fapi2::ReturnCode change_force_mclk_low (const fapi2::Target<fapi2::TARGET_TYPE_
             l_data.clearBit<MCA_MBA_FARB5Q_CFG_FORCE_MCLK_LOW_N>();
         }
 
-        FAPI_TRY(fapi2::putScom( p, MCA_MBA_FARB5Q, l_data));
+        FAPI_TRY(mss::putScom( p, MCA_MBA_FARB5Q, l_data));
     }
 
 fapi_try_exit:
@@ -399,7 +399,7 @@ fapi2::ReturnCode ddr_phy_flush( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targ
 
     for (auto p : l_ports)
     {
-        FAPI_TRY(fapi2::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, l_data, l_mask) );
+        FAPI_TRY(mss::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, l_data, l_mask) );
     }
 
     fapi2::delay(DELAY_100NS, cycles_to_simcycles(ns_to_cycles(i_target, 100)));
@@ -408,7 +408,7 @@ fapi2::ReturnCode ddr_phy_flush( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targ
 
     for (auto p : l_ports)
     {
-        FAPI_TRY(fapi2::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, 0, l_mask) );
+        FAPI_TRY(mss::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, 0, l_mask) );
     }
 
 fapi_try_exit:
@@ -435,7 +435,7 @@ static inline fapi2::ReturnCode phy_block_broadcast( const fapi2::Target<TARGET_
     // the PHY) we can use the broadcast bits and iterate over the DIMM ranks.
     for (size_t i = 0; i < PHY_INSTANCE_COUNT; ++i)
     {
-        FAPI_TRY( fapi2::putScom(i_target, l_addr | fapi2::buffer<uint64_t>().insertFromRight<18, 4>(i), i_data) );
+        FAPI_TRY( mss::putScom(i_target, l_addr | fapi2::buffer<uint64_t>().insertFromRight<18, 4>(i), i_data) );
     }
 
 fapi_try_exit:
@@ -540,25 +540,25 @@ fapi2::ReturnCode rank_pair_primary_to_dimm(
     switch(i_rp)
     {
         case 0:
-            FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) );
+            FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) );
             l_data.extractToRight<MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI,
                                   MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN>(l_rank);
             break;
 
         case 1:
-            FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) );
+            FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) );
             l_data.extractToRight<MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI,
                                   MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN>(l_rank);
             break;
 
         case 2:
-            FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) );
+            FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) );
             l_data.extractToRight<MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI,
                                   MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN>(l_rank);
             break;
 
         case 3:
-            FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) );
+            FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) );
             l_data.extractToRight<MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI,
                                   MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN>(l_rank);
             break;
@@ -599,7 +599,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC
 
     fapi2::Target<TARGET_TYPE_DIMM> l_failed_dimm;
 
-    FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_APB_FIR_ERR1_P0, l_fir_data) );
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_APB_FIR_ERR1_P0, l_fir_data) );
 
     FAPI_DBG("initial cal FIR: 0x%016llx", uint64_t(l_fir_data));
 
@@ -609,7 +609,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC
     }
 
     // We have bits to check ...
-    FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, l_err_data) );
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_INIT_CAL_ERROR_P0, l_err_data) );
 
     l_err_data.extractToRight<MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL, 11>(l_errors);
     l_err_data.extractToRight<MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR,
@@ -761,7 +761,7 @@ template<>
 fapi2::ReturnCode set_pc_config0(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
 {
     fapi2::buffer<uint64_t> l_data;
-    FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
 
     // Note: This needs to get the DRAM gen from an attribute. - 0x1 is DDR4 Note for Nimbus PHY
     // this is ignored and hard-wired to DDR4, per John Bialas 10/15 BRS
@@ -771,7 +771,7 @@ fapi2::ReturnCode set_pc_config0(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     l_data.setBit<MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP>();
 
     FAPI_DBG("phy pc_config0 0x%0llx", l_data);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -820,7 +820,7 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     l_gen_index = l_dram_gen[0] | l_dram_gen[1];
 
     // FOR NIMBUS PHY (as the protocol choice above is) BRS
-    FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
 
     l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE,
                            MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN>(memory_type[l_type_index][l_gen_index]);
@@ -832,7 +832,7 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     l_data.setBit<MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW>();
 
     FAPI_DBG("phy pc_config1 0x%0llx", l_data);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index dd7ee3fa4..eff335982 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -35,7 +35,7 @@
 
 // Helper macro to condense the checking for PLL lock
 #define CHECK_PLL( __target, __register, __buffer, __mask )             \
-    FAPI_TRY(fapi2::getScom( __target, __register, __buffer));          \
+    FAPI_TRY(mss::getScom( __target, __register, __buffer));          \
     if ((__buffer & __mask) != __mask)                                  \
     {                                                                   \
         FAPI_INF("PLL 0x%lx failed to lock 0x%lx", __register, __buffer); \
@@ -331,7 +331,7 @@ inline fapi2::ReturnCode dump_cal_registers( const fapi2::Target<fapi2::TARGET_T
     for (auto r : l_registers)
     {
         fapi2::buffer<uint64_t> l_data;
-        FAPI_TRY( fapi2::getScom(i_target, r.first, l_data) );
+        FAPI_TRY( mss::getScom(i_target, r.first, l_data) );
         FAPI_DBG("dump %s: 0x%llx 0x%llx", r.second, r.first, l_data);
     }
 
@@ -401,7 +401,7 @@ inline fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYP
     }
 
     FAPI_INF("cal_config for %s: 0x%llx", mss::c_str(i_target), l_cal_config);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, l_cal_config) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, l_cal_config) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -463,7 +463,7 @@ inline fapi2::ReturnCode reset_wc_config0( const fapi2::Target<fapi2::TARGET_TYP
     l_data.clearBit<MCA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE>();
 
     FAPI_DBG("wc_config0 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target));
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG0_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG0_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -497,7 +497,7 @@ inline fapi2::ReturnCode reset_wc_config1( const fapi2::Target<fapi2::TARGET_TYP
     l_data.insertFromRight<MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP, MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN>(WR_LVL_SMALL_STEP);
     l_data.insertFromRight<MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY,
                            MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN>(WR_LVL_PRE_DLY);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG1_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG1_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -529,7 +529,7 @@ inline fapi2::ReturnCode reset_wc_config2( const fapi2::Target<fapi2::TARGET_TYP
 
     l_data.insertFromRight<MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR, MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN>(WR_CNTR_FW_RD_WR);
 
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -569,7 +569,7 @@ inline fapi2::ReturnCode reset_wc_config3( const fapi2::Target<fapi2::TARGET_TYP
                                MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN>(CMD_DQ_OFF);
     }
 
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG3_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG3_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -600,7 +600,7 @@ inline fapi2::ReturnCode reset_seq_config0( const fapi2::Target<fapi2::TARGET_TY
     // ATTR_VPD_DRAM_2N_MODE_ENABLED  49, 0b1, (def_2N_mode);       # enable 2 cycle addr mode BRS
 
     FAPI_DBG("seq_config0 0x%llx", l_data);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_CONFIG0_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_CONFIG0_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -649,7 +649,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1,
                                MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN>(l_odt_rd[0][1]);
         FAPI_DBG("odt_rd_config0: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0, l_data) );
     }
 
     {
@@ -663,7 +663,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3,
                                MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN>(l_odt_rd[0][3]);
         FAPI_DBG("odt_rd_config1: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0, l_data) );
     }
 
     {
@@ -677,7 +677,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5,
                                MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5_LEN>(l_odt_rd[1][1]);
         FAPI_DBG("odt_rd_config2: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0, l_data) );
     }
 
     {
@@ -691,7 +691,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7,
                                MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7_LEN>(l_odt_rd[1][3]);
         FAPI_DBG("odt_rd_config3: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0, l_data) );
     }
 
     //
@@ -708,7 +708,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1,
                                MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN>(l_odt_wr[0][1]);
         FAPI_DBG("odt_wr_config0: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0, l_data) );
     }
 
     {
@@ -722,7 +722,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3,
                                MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN>(l_odt_wr[0][3]);
         FAPI_DBG("odt_wr_config1: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0, l_data) );
     }
 
     {
@@ -736,7 +736,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5,
                                MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5_LEN>(l_odt_wr[1][1]);
         FAPI_DBG("odt_wr_config2: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0, l_data) );
     }
 
     {
@@ -750,7 +750,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
         l_data.insertFromRight<MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7,
                                MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7_LEN>(l_odt_wr[1][3]);
         FAPI_DBG("odt_wr_config3: 0x%016llx", uint64_t(l_data));
-        FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0, l_data) );
+        FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0, l_data) );
     }
 
 fapi_try_exit:
@@ -786,8 +786,8 @@ inline fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<fapi2::TARGET
                            MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN>(MPR_PATTERN);
 
     FAPI_DBG("seq_rd_wr 0x%llx", l_data);
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA0_P0, l_data) );
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA1_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA0_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA1_P0, l_data) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 81e50fc8c..8f171e7ff 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -31,6 +31,7 @@
 #include <utility>
 #include <vector>
 
+#include "../utils/scom.H"
 #include "dp16.H"
 
 #include <p9_mc_scom_addresses.H>
@@ -163,7 +164,7 @@ fapi2::ReturnCode write_data_bit_enable( const fapi2::Target<TARGET_TYPE_MCA>& i
     {
         // This is probably important enough to be seen all the time, not just debug
         FAPI_INF( "Setting up DATA_BIT_ENABLE 0x%llx (0x%llx) %s", rdp.first, rdp.second, mss::c_str(i_target) );
-        FAPI_TRY( fapi2::putScom(i_target, rdp.first, rdp.second) );
+        FAPI_TRY( mss::putScom(i_target, rdp.first, rdp.second) );
     }
 
 fapi_try_exit:
@@ -196,7 +197,7 @@ fapi2::ReturnCode read_clock_enable( const fapi2::Target<TARGET_TYPE_MCA>& i_tar
             l_data.insertFromRight<MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16, 16>(rdp.second);
 
             FAPI_INF( "Setting up RDCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) );
-            FAPI_TRY( fapi2::putScom(i_target, l_address, l_data) );
+            FAPI_TRY( mss::putScom(i_target, l_address, l_data) );
         }
     }
 
@@ -230,7 +231,7 @@ fapi2::ReturnCode write_clock_enable( const fapi2::Target<TARGET_TYPE_MCA>& i_ta
             l_data.insertFromRight<MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16, 16>(rdp.second);
 
             FAPI_INF( "Setting up WRCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) );
-            FAPI_TRY( fapi2::putScom(i_target, l_address, l_data) );
+            FAPI_TRY( mss::putScom(i_target, l_address, l_data) );
         }
     }
 
@@ -261,9 +262,9 @@ fapi2::ReturnCode reset_delay_values( const fapi2::Target<TARGET_TYPE_MCA>& i_ta
 
     // Reset the write level values
     FAPI_INF( "Resetting write level values %s", mss::c_str(i_target) );
-    FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
     l_data.setBit<MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL>();
-    FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) );
 
     for (auto rp : l_rank_pairs)
     {
@@ -274,7 +275,7 @@ fapi2::ReturnCode reset_delay_values( const fapi2::Target<TARGET_TYPE_MCA>& i_ta
             l_address.insertFromRight<22, 2>(rp);
 
             FAPI_DBG( "Resetting DP16 gate delay 0x%llx %s", l_address, mss::c_str(i_target) );
-            FAPI_TRY( fapi2::putScom(i_target, l_address, 0) );
+            FAPI_TRY( mss::putScom(i_target, l_address, 0) );
         }
     }
 
@@ -316,8 +317,8 @@ fapi2::ReturnCode setup_sysclk( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
 
         for (auto a : l_addrs)
         {
-            FAPI_TRY( fapi2::putScom(p, a.first, l_data) );
-            FAPI_TRY( fapi2::putScom(p, a.second, l_data) );
+            FAPI_TRY( mss::putScom(p, a.first, l_data) );
+            FAPI_TRY( mss::putScom(p, a.second, l_data) );
         }
     }