Implementing draminit_training_adv

    Set default pattern to john's new one and backup to supernova 2.0

Change-Id: I406bb5c5652cff9fe4690e5bd9b03cc431d75f61
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44709
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44780
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

8 files changed, 318 insertions, 21 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
index 16f87310f..e901055e8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
@@ -237,7 +237,11 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target,
     l_total_cycles = i_cal_steps_enabled.getBit<WR_LEVEL>()     ? wr_lvl_cycles(i_target)      : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<DQS_ALIGN>()   ? dqs_align_cycles(i_target)   : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<RDCLK_ALIGN>() ? rdclk_align_cycles(i_target) : 0;
-    l_total_cycles += i_cal_steps_enabled.getBit<READ_CTR>()    ? read_ctr_cycles(i_target)    : 0;
+
+    // We run either read centering during normal draminit_training and also during draminit_training_advance,
+    // can't be run twice in one cal though
+    l_total_cycles += ( i_cal_steps_enabled.getBit<READ_CTR>() || i_cal_steps_enabled.getBit<TRAINING_ADV>())
+                      ? read_ctr_cycles(i_target)    : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<WRITE_CTR>()   ? l_write_cntr_cycles          : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<COARSE_WR>()   ? coarse_wr_cycles(i_target)   : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<COARSE_RD>()   ? coarse_rd_cycles(i_target)   : 0;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 5d8aaf71f..bd920c3a3 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -700,6 +700,7 @@ fapi_try_exit:
 /// @param[in] i_target the port target
 /// @param[in] i_rp the rank pair we are calibrating
 /// @param[in] i_cal_abort_on_error denoting if we aborted on first fail
+/// @param[out] o_cal_fail a flag that gets set to true if there was a cal fail
 /// @param[in,out] io_fails a vector storing all of our cal fails
 /// @return FAPI2_RC_SUCCESS iff all of the scoms and functionality were good
 ///
@@ -707,6 +708,7 @@ template<>
 fapi2::ReturnCode find_and_log_cal_errors(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
         const uint64_t i_rp,
         const uint64_t i_cal_abort_on_error,
+        bool& o_cal_fail,
         std::vector<fapi2::ReturnCode>& io_fails)
 {
     fapi2::ReturnCode l_rc (fapi2::FAPI2_RC_SUCCESS);
@@ -725,6 +727,8 @@ fapi2::ReturnCode find_and_log_cal_errors(const fapi2::Target<fapi2::TARGET_TYPE
 
     if (l_rc != fapi2::FAPI2_RC_SUCCESS)
     {
+        o_cal_fail = true;
+
         // If we're aborting on error we jump to the end and error out.
         // We don't care about other ports or ranks because the hardware stopped when it saw the error
         if (i_cal_abort_on_error)
@@ -799,8 +803,6 @@ fapi2::ReturnCode draminit_training_error_handler( const std::vector<fapi2::Retu
         fapi2::logError(l_iter, fapi2::FAPI2_ERRL_SEV_RECOVERED);
     }
 
-    return fapi2::current_err;
-
 // If we're cronus, let's bomb out
 #else
 
@@ -954,7 +956,8 @@ fapi2::ReturnCode setup_read_vref_config1( const fapi2::Target<fapi2::TARGET_TYP
     l_data.writeBit<TT::RDVREF_CALIBRATION_ENABLE>( i_cal_steps_enabled.getBit<READ_CTR_2D_VREF>() );
 
     // Check to see if READ_CENTERING is disabled, if so, set the bit
-    l_data.writeBit<TT::SKIP_RDCENTERING>( !i_cal_steps_enabled.getBit<READ_CTR>() );
+    l_data.writeBit<TT::SKIP_RDCENTERING>( !(i_cal_steps_enabled.getBit<READ_CTR>()
+                                           || i_cal_steps_enabled.getBit<TRAINING_ADV>()) );
 
     FAPI_INF("%s %s read VREF cal, read centering is %s",
              mss::c_str(i_target),
@@ -986,9 +989,8 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
     FAPI_TRY( mss::is_simulation(l_sim) );
 
     // This is the buffer which will be written to CAL_CONFIG0. It starts
-    // life assuming no cal sequences, no rank pairs - but we set the abort-on-error
-    // bit ahead of time.
-    l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR>(l_cal_abort_on_error);
+    // life assuming no cal sequences, no rank pairs
+
 
     // Sadly, the bits in the register don't align directly with the bits in the attribute.
     // So, arrange the bits accordingly and write the config register.
@@ -1010,12 +1012,29 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
         l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD>(
             i_cal_steps_enabled.getBit<COARSE_RD>());
 
-        // Always turn on initial pattern write in h/w, never for sim (makes the DIMM behavioral lose it's mind)
+        // Turn on initial pattern write only in h/w, never for sim (makes the DIMM behavioral lose it's mind)
         if (!l_sim)
         {
+            // If we are running training advance, none of the steps above can be enabled.
+            // If they are, we have a code bug and should fapi2:Assert.
+            // This isn't dependent on system or attributes but code structure
+            if ( l_cal_config != 0 && i_cal_steps_enabled.getBit<TRAINING_ADV>())
+            {
+                FAPI_ERR("Error setting up draminit training advance. Set CUSTOM_RD with other cal steps");
+                fapi2::Assert( false );
+            }
+
+            // Enable CUSTOM_RD for training ADV. If this bit is set, only TRAINING_ADV and INIT_PAT_WR can be set
+            // We assert this above.
+            l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD>(
+                i_cal_steps_enabled.getBit<TRAINING_ADV>());
+
             l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR>(
                 i_cal_steps_enabled.getBit<INITIAL_PAT_WR>());
         }
+
+        // Moved this down here so we can make the training advance check above
+        l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR>(l_cal_abort_on_error);
     }
 
     // Blast the VREF config with the proper setting for these cal bits if there were any enable bits set
@@ -1083,7 +1102,7 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
         FAPI_TRY( l_cal_config.setBit(MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR + rp) );
     }
 
-    FAPI_INF("cal_config for %s: 0x%04lx (steps: 0x%08lx)",
+    FAPI_INF("cal_config for %s: 0x%04lx (steps: 0x%08x)",
              mss::c_str(i_target), uint16_t(l_cal_config), uint32_t(i_cal_steps_enabled));
     FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, l_cal_config) );
 
@@ -1215,7 +1234,10 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         }
 
         // Execute WR_LEVEL
-        FAPI_TRY( execute_cal_steps_helper(i_target, i_rp, l_steps_to_execute, i_abort_on_error) );
+        FAPI_TRY( execute_cal_steps_helper(i_target,
+                                           i_rp,
+                                           l_steps_to_execute,
+                                           i_abort_on_error) );
 
         // Restore normal terminations
         l_rtt_inst.clear();
@@ -1223,21 +1245,28 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
 
         if (!l_rtt_inst.empty())
         {
-            l_program.iv_instructions.insert(l_program.iv_instructions.end(), l_rtt_inst.begin(), l_rtt_inst.end() );
+            l_program.iv_instructions.insert(l_program.iv_instructions.end(),
+                                             l_rtt_inst.begin(),
+                                             l_rtt_inst.end() );
             FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target) );
         }
     }
 
-    // run Initial Pattern Write
+    // run Initial Pattern Write and custom read centering if enabled
     if(i_cal_steps_enabled.getBit<mss::cal_steps::INITIAL_PAT_WR>())
     {
         // Sets up the cal steps in the buffer
         fapi2::buffer<uint32_t> l_steps_to_execute;
         l_steps_to_execute.writeBit<mss::cal_steps::INITIAL_PAT_WR>
         (i_cal_steps_enabled.getBit<mss::cal_steps::INITIAL_PAT_WR>());
+        l_steps_to_execute.writeBit<mss::cal_steps::TRAINING_ADV>
+        (i_cal_steps_enabled.getBit<mss::cal_steps::TRAINING_ADV>());
 
-        FAPI_INF("%s Running Initial Pattern Write on RP%d 0x%08lx",
-                 mss::c_str(i_target), i_rp, l_steps_to_execute);
+        FAPI_INF("%s Running Initial Pattern Write and TRAINING_ADV(%s) on RP%d 0x%08x",
+                 mss::c_str(i_target),
+                 (i_cal_steps_enabled.getBit<mss::cal_steps::TRAINING_ADV>() ? "yes" : "no"),
+                 i_rp,
+                 l_steps_to_execute);
 
         // Undertake the calibration steps
         FAPI_TRY( execute_cal_steps_helper(i_target, i_rp, l_steps_to_execute, i_abort_on_error) );
@@ -1250,7 +1279,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         fapi2::buffer<uint32_t> l_steps_to_execute;
         l_steps_to_execute.setBit<mss::cal_steps::DQS_ALIGN>();
 
-        FAPI_INF("%s Running DQS align on RP%d 0x%08lx",
+        FAPI_INF("%s Running DQS align on RP%d 0x%08x",
                  mss::c_str(i_target), i_rp, l_steps_to_execute);
 
         // Undertake the calibration steps
@@ -1274,7 +1303,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
                                     mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN,
                                     mss::cal_steps::RDCLK_ALIGN>(l_steps_to_execute);
 
-        FAPI_INF("%s Running rd_clk align through read centering vref on RP%d 0x%08lx", mss::c_str(i_target), i_rp,
+        FAPI_INF("%s Running rd_clk align through read centering vref on RP%d 0x%08x", mss::c_str(i_target), i_rp,
                  l_steps_to_execute);
 
         // Undertake the calibration steps
@@ -1292,7 +1321,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
     }
 
     // Run cal steps after RD_CTR if any are selected - note: WRITE_CTR takes place after RD_CTR
-    if (i_cal_steps_enabled.getBit<mss::cal_steps::WRITE_CTR, mss::cal_steps::WR_VREF_TO_COARSE_RD_LEN>())
+    if (i_cal_steps_enabled.getBit<mss::cal_steps::WRITE_CTR_2D_VREF, mss::cal_steps::WR_VREF_TO_COARSE_RD_LEN>())
     {
         fapi2::buffer<uint32_t> l_steps_to_execute( i_cal_steps_enabled );
         l_steps_to_execute.clearBit<mss::cal_steps::DRAM_ZQCAL, mss::cal_steps::DRAM_ZQCAL_UP_TO_WRITE_CTR_2D_VREF>();
@@ -1301,7 +1330,7 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         // Gets set iff the bit is set in i_steps_to_execute
         l_steps_to_execute.writeBit<WR_VREF_LATCH>( i_cal_steps_enabled.getBit<WR_VREF_LATCH>() );
 
-        FAPI_DBG("%s Running remaining cal steps on RP%d 0x%08lx", mss::c_str(i_target), i_rp, l_steps_to_execute);
+        FAPI_DBG("%s Running remaining cal steps on RP%d 0x%08x", mss::c_str(i_target), i_rp, l_steps_to_execute);
 
         FAPI_TRY( execute_cal_steps_helper(i_target, i_rp, l_steps_to_execute, i_abort_on_error) );
     }
@@ -1783,6 +1812,34 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Set the custom pattern
+/// @param[in] i_target the port target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template<>
+fapi2::ReturnCode configure_custom_pattern( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    uint32_t l_pattern = 0;
+    uint32_t l_swizzled = 0;
+
+    // Set the custom patterns for training advance
+    // So first get the pattern from the attribute and then put it into the register
+
+    FAPI_TRY( mss::custom_training_adv_patterns( i_target, l_pattern) );
+    FAPI_TRY( mss::seq::swizzle_mpr_pattern(l_pattern, l_swizzled) );
+
+    FAPI_INF("%s the patterns before swizzle are 0x%08x and after 0x%08x",
+             mss::c_str(i_target),
+             l_pattern,
+             l_swizzled);
+
+    FAPI_TRY( mss::seq::setup_rd_wr_data( i_target, l_swizzled) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Flush the output drivers
 /// @param[in] i_target the target associated with the phy reset sequence
 /// @return FAPI2_RC_SUCCESS iff setup was successful
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index 39db82147..e111d9778 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -424,6 +424,13 @@ fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target<fapi2::TARGET_TYPE_M
 template<fapi2::TargetType T>
 fapi2::ReturnCode rank_pair_primary_to_dimm(const fapi2::Target<T>& i_target, const uint64_t i_rp,
         fapi2::Target<fapi2::TARGET_TYPE_DIMM>& o_dimm);
+///
+/// @brief Set the custom pattern
+/// @param[in] i_target the port target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode configure_custom_pattern( const fapi2::Target<T>& i_target );
 
 ///
 /// @brief Handle draminit_training cal fails
@@ -440,6 +447,7 @@ fapi2::ReturnCode draminit_training_error_handler ( const std::vector<fapi2::Ret
 /// @param[in] i_target the port target
 /// @param[in] i_rp the rank pair we are calibrating
 /// @param[in] i_cal_abort_on_error denoting if we aborted on first fail
+/// @param[out] o_cal_fail a flag that gets set to true if there was a cal fail
 /// @param[in,out] io_fails a vector storing all of our cal fails
 /// @return FAPI2_RC_SUCCESS iff all of the scoms and functionality were good
 ///
@@ -447,6 +455,7 @@ template<fapi2::TargetType T>
 fapi2::ReturnCode find_and_log_cal_errors(const fapi2::Target<T>& i_target,
         const uint64_t i_rp,
         const uint64_t i_cal_abort_on_error,
+        bool& o_cal_fail,
         std::vector<fapi2::ReturnCode>& io_fails);
 
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index eebb2b5f1..b6e2782a9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -252,6 +252,18 @@ const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::IO_TX_PFET_TERM_REG
     MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4,
 };
 
+// Receiver configuration for the DP16.
+const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DP16_RX_REGS
+{
+    {
+        MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0,
+        MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1,
+        MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2,
+        MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3,
+        MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4,
+    },
+};
+
 // Definition of the DD1 DP16 RD_VREF Control registers
 // Note: For DD2 if we use the DD2_PERBIT_RDVREF_DISABLE, then these registers are still valid
 // DP16 RD_VREF Control registers all come in pairs - one per 8 bits
@@ -267,6 +279,7 @@ const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DD1_RD_VREF_CNTRL_REG
     },
 };
 
+
 // Definition of the DD2 DP16 RD_VREF Control registers
 // Note: DO NOT use this for DD1 as it will lead to a runtime scom access error
 // DD2 DP16 RD_VREF Control registers all come in one register per pair of bits
@@ -1401,11 +1414,38 @@ fapi_try_exit:
 };
 
 ///
-/// @brief Reset CTLE_CNTL MCA specialization - for all DP16 in the target
+/// @brief Set RX_CONFIG0_P0_DP16_0_READ_CENTERING_MODE - for all DP16 in the target
 /// @param[in] i_target the fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
 ///
 template<>
+fapi2::ReturnCode setup_custom_read_centering_mode( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
+{
+    typedef dp16Traits<TARGET_TYPE_MCA> TT;
+
+    constexpr uint8_t CUSTOM_READ_CENTERING = 0b11;
+    std::vector< fapi2::buffer< uint64_t > > l_data;
+
+    const auto& DP16_RX_REGS = TT::DP16_RX_REGS;
+    FAPI_TRY( mss::scom_suckah(i_target, DP16_RX_REGS, l_data) );
+
+    for (auto& l_reg_data : l_data)
+    {
+        l_reg_data.insertFromRight<TT::READ_CENTERING_MODE, TT::READ_CENTERING_MODE_LEN>(CUSTOM_READ_CENTERING);
+        FAPI_INF("%s setting custom read centering mode 0x%016lx", mss::c_str(i_target), l_reg_data);
+    }
+
+    FAPI_TRY( mss::scom_blastah(i_target, DP16_RX_REGS, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Reset CTLE_CNTL MCA specialization - for all DP16 in the target
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+template<>
 fapi2::ReturnCode reset_ctle_cntl( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
 {
     typedef dp16Traits<TARGET_TYPE_MCA> TT;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 4b2a7a2d0..8c1c752dc 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -180,6 +180,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
         static const std::vector< uint64_t > DD1_RD_VREF_CNTRL_REG;
         static const std::vector< uint64_t > DD2_RD_VREF_CNTRL_REG;
         static const std::vector< uint64_t > DRIFT_LIMITS_REG;
+        static const std::vector< uint64_t > DP16_RX_REGS;
 
         static const std::vector<std::vector<std::pair<uint64_t, uint64_t>>> BIT_DISABLE_REG;
 
@@ -205,6 +206,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
         static const std::vector< uint64_t > RD_STATUS0_REG;
         static const std::vector< uint64_t > WR_ERROR0_REG;
 
+
         // Definitions of the gate delay and waterfall bits' locations
         constexpr static const uint64_t GATE_DELAY_BIT_POS[NUM_QUAD_PER_DP16] =
         {
@@ -223,6 +225,10 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
 
         enum
         {
+            // Name changes for dd2 to P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0
+            READ_CENTERING_MODE = MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE,
+            READ_CENTERING_MODE_LEN = MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE_LEN,
+
             DLL_CNTL_INIT_RXDLL_CAL_RESET = MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET,
             DLL_CNTL_INIT_RXDLL_CAL_SKIP = MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP,
             DLL_CNTL_INIT_RXDLL_CAL_SKIP_LEN = MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN,
@@ -2115,6 +2121,16 @@ inline void set_blue_waterfall_range( const fapi2::Target<T>& i_target,
 }
 
 ///
+/// @brief Set RX_CONFIG0_P0_DP16_0_READ_CENTERING_MODE
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = dp16Traits<T> >
+fapi2::ReturnCode setup_custom_read_centering_mode( const fapi2::Target<T>& i_target );
+
+///
 /// @brief Reset rd_lvl_status0 registers
 /// @tparam T fapi2 Target Type - derived
 /// @tparam TT traits type defaults to dp16Traits<T>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 055f0ba1d..e19067ed4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -318,6 +318,26 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Set STAGGERED_PATTERN bit in read_config0
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = rcTraits<T> >
+inline fapi2::ReturnCode change_staggered_pattern( const fapi2::Target<T>& i_target)
+{
+    fapi2::buffer<uint64_t> l_data;
+    FAPI_TRY( read_config0( i_target, l_data) );
+
+    l_data.setBit<TT::STAGGERED_PATTERN>();
+
+    FAPI_TRY( write_config0( i_target, l_data) );
+
+    FAPI_DBG("%s set staggered_pattern rc_config0: 0x%016llx", mss::c_str(i_target), l_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief reset rc_config0
 /// @param[in] i_target fapi2 target of the port
 /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
index 8c5f0b02d..e506abb02 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C
@@ -39,6 +39,7 @@
 #include <generic/memory/lib/utils/c_str.H>
 #include <lib/utils/bit_count.H>
 #include <lib/eff_config/timing.H>
+#include <lib/shared/mss_const.H>
 
 using fapi2::TARGET_TYPE_MCA;
 using fapi2::TARGET_TYPE_DIMM;
@@ -174,6 +175,35 @@ fapi2::ReturnCode reset_timing1( const fapi2::Target<TARGET_TYPE_MCA>& i_target
     return mss::putScom(i_target, TT::SEQ_TIMING1_REG, l_data);
 }
 
+///
+/// @brief Swizzle the MPR pattern to switch bit order in each byte
+/// @param[in] i_patterns the patterns to put in SEQ_RDWR_DATA0 and _DATA1 registers
+/// @param[out] The swizzle pattern
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+fapi2::ReturnCode swizzle_mpr_pattern( const uint32_t i_pattern, uint32_t& o_swizzled)
+{
+    constexpr uint64_t BYTES_PER_32 = 4;
+    fapi2::buffer<uint32_t> l_buf (i_pattern);
+
+    // loop over each byte and reverse the bits
+    for (size_t count = 0; count < BYTES_PER_32; ++count)
+    {
+        fapi2::buffer<uint8_t> l_temp;
+        FAPI_TRY( l_buf.extract(l_temp, count * BITS_PER_BYTE, BITS_PER_BYTE) );
+
+        // reverse is in swizzle.H. Reverses all of the bits in the buffer
+        mss::reverse(l_temp);
+        FAPI_TRY( l_buf.insert(l_temp, count * BITS_PER_BYTE, BITS_PER_BYTE) );
+    }
+
+    o_swizzled = l_buf;
+
+    FAPI_INF("0x%08x unswizzle 0x%08x swizzled that dizzle", i_pattern, o_swizzled);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
 
 ///
 /// @brief reset SEQ_TIMING2
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
index 3386b9b09..a310cde85 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H
@@ -357,6 +357,80 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Read SEQ_RDWR_DATA0 register
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_rd_wr_data0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_RDWR_DATA0, o_data), "%s failed to read rd_wr_data0 register",
+              mss::c_str(i_target) );
+    FAPI_DBG("%s read rd_wr_data0: 0x%016lx", mss::c_str(i_target), o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write SEQ_RDWR_DATA0 register
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_rd_wr_data0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("%s write rd_wr_data0: 0x%016lx", mss::c_str(i_target), i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, i_data), "%s failed to write seq_rd_wr_data0 register",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Read SEQ_RDWR_DATA1 register
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode read_rd_wr_data1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    FAPI_TRY( mss::getScom(i_target, TT::SEQ_RDWR_DATA1, o_data), "%s failed to read rd_wr_data1 register",
+              mss::c_str(i_target) );
+    FAPI_DBG("%s rd_wr_data1: 0x%016lx", mss::c_str(i_target), o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write SEQ_RDWR_DATA1 register
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the fapi2 target of the port
+/// @param[in] i_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+inline fapi2::ReturnCode write_rd_wr_data1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    FAPI_DBG("%s write rd_wr_data1: 0x%016lx", mss::c_str(i_target), i_data);
+    FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, i_data), "%s failed to write seq_rd_wr_data1 register",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief Setup odt_wr/rd_config
 /// @tparam T fapi2 Target Type - derived
 /// @tparam TT traits type defaults to seqTraits<T>
@@ -383,12 +457,12 @@ fapi2::ReturnCode reset_rd_wr_data( const fapi2::Target<T>& i_target )
     fapi2::buffer<uint64_t> l_data;
 
     l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR01_PATTERN);
-    FAPI_INF("seq_rd_wr0 0x%llx", l_data);
+    FAPI_INF("%s seq_rd_wr0 0x%llx", mss::c_str(i_target), l_data);
     FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA0, l_data), "%s failed to reset seq_rd_wr0 register via write",
               mss::c_str(i_target) );
 
     l_data.insertFromRight<TT::MPR_PATTERN, TT::MPR_PATTERN_LEN>(MPR23_PATTERN);
-    FAPI_INF("seq_rd_wr1 0x%llx", l_data);
+    FAPI_INF("%s seq_rd_wr1 0x%llx", mss::c_str(i_target), l_data);
     FAPI_TRY( mss::putScom(i_target, TT::SEQ_RDWR_DATA1, l_data), "%s failed to reset seq_rd_wr1 register via write",
               mss::c_str(i_target) );
 
@@ -397,6 +471,53 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Swizzle the MPR pattern for the register
+/// @param[in] i_patterns the patterns to put in SEQ_RDWR_DATA0 and _DATA1 registers
+/// @param[out] The swizzled pattern
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+fapi2::ReturnCode swizzle_mpr_pattern( const uint32_t i_pattern, uint32_t& o_swizzled);
+
+///
+/// @brief Setup odt_wr/rd_config
+/// @tparam T fapi2 Target Type - derived
+/// @tparam TT traits type defaults to seqTraits<T>
+/// @param[in] i_target the target associated with this cal setup
+/// @param[in] i_patterns the patterns to put in SEQ_RDWR_DATA0 and _DATA1 registers
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template< fapi2::TargetType T, typename TT = seqTraits<T> >
+fapi2::ReturnCode setup_rd_wr_data( const fapi2::Target<T>& i_target, const uint32_t i_patterns)
+{
+    fapi2::buffer<uint32_t> l_data (i_patterns);
+    fapi2::buffer<uint64_t> l_temp;
+
+
+    FAPI_TRY( read_rd_wr_data0(i_target, l_temp),
+              "%s failed to reading rd_wr_data",
+              mss::c_str(i_target) );
+
+    l_data.extractToRight<mss::PATTERN0_START, mss::PATTERN0_LEN>(l_temp);
+
+    FAPI_TRY( write_rd_wr_data0(i_target, l_temp),
+              "%s failed to writing rd_wr_data",
+              mss::c_str(i_target) );
+
+    FAPI_TRY( read_rd_wr_data1(i_target, l_temp),
+              "%s failed to read rd_wr0 register via write",
+              mss::c_str(i_target) );
+
+    l_data.extractToRight<mss::PATTERN1_START, mss::PATTERN1_LEN>(l_temp);
+
+    FAPI_TRY( write_rd_wr_data1(i_target, l_temp),
+              "%s failed to write seq_rd_wr1 register via write",
+              mss::c_str(i_target) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief reset SEQ_CONFIG0
 /// @tparam T fapi2 Target Type - derived
 /// @tparam TT traits type defaults to seqTraits<T>