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| author | Louis Stermole <stermole@us.ibm.com> | 2017-11-07 07:16:09 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-21 17:00:09 -0500 |
| commit | d7750b78d80c3527bcb5235b8c94ccd5613d5f60 (patch) | |
| tree | 20347553e9f9944a4138a5c7782521bf34958ec2 /src/import/chips/p9/procedures/hwp/memory/lib/phy | |
| parent | dc276ea88de6962710917267975cc3d71e8076ea (diff) | |
| download | talos-hostboot-d7750b78d80c3527bcb5235b8c94ccd5613d5f60.tar.gz talos-hostboot-d7750b78d80c3527bcb5235b8c94ccd5613d5f60.zip | |
Fix tWLDQSEN and IPW_WR_WR timing parameters for MSS training
Change-Id: Iee425c7c404720275f3789436c698892e39842c2
CQ: SW407830
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49352
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49358
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H | 6 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C index e506abb02..6c61d08ce 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.C @@ -167,12 +167,18 @@ fapi2::ReturnCode reset_timing1( const fapi2::Target<TARGET_TYPE_MCA>& i_target // TWRMRD_CYCLES tWLMRD uint64_t l_tzqint = std::max( mss::tzqinit(), mss::tzqoper() ); + uint8_t l_twldqsen = 0; + FAPI_TRY( mss::twldqsen(i_target, l_twldqsen), "%s Failed to calculate tWLDQSEN", mss::c_str(i_target) ); + l_data.insertFromRight<TT::TZQINIT_CYCLES, TT::TZQINIT_CYCLES_LEN>( exp_helper(l_tzqint) ); l_data.insertFromRight<TT::TZQCS_CYCLES, TT::TZQCS_CYCLES_LEN>( exp_helper(mss::tzqcs()) ); - l_data.insertFromRight<TT::TWLDQSEN_CYCLES, TT::TWLDQSEN_CYCLES_LEN>( exp_helper(mss::twldqsen()) ); + l_data.insertFromRight<TT::TWLDQSEN_CYCLES, TT::TWLDQSEN_CYCLES_LEN>( exp_helper(l_twldqsen) ); l_data.insertFromRight<TT::TWRMRD_CYCLES, TT::TWRMRD_CYCLES_LEN>( exp_helper(mss::twlmrd()) ); - return mss::putScom(i_target, TT::SEQ_TIMING1_REG, l_data); + FAPI_TRY( mss::putScom(i_target, TT::SEQ_TIMING1_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H index 9e4da36a0..57cb9b34f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H @@ -397,10 +397,16 @@ inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target ) fapi2::buffer<uint64_t> l_data; uint8_t l_fw_rd_wr = 0; + // Memory clock cycle separation value for write commands during Initial Pattern Write. + // This value needs to be set to 5 to get the desired value of 24 clock cycles. + // (ipw_wr_wr + 1) * 4 = 24 + constexpr uint64_t IPW_WR_WR = 5; + FAPI_TRY( mss::fw_rd_wr(i_target, l_fw_rd_wr) ); l_data.insertFromRight<TT::NUM_VALID_SAMPLES, TT::NUM_VALID_SAMPLES_LEN>(WR_LVL_NUM_VALID_SAMPLES); l_data.insertFromRight<TT::FW_RD_WR, TT::FW_RD_WR_LEN>(l_fw_rd_wr); + l_data.insertFromRight<TT::IPW_WR_WR, TT::IPW_WR_WR_LEN>(IPW_WR_WR); FAPI_DBG("%s wc_config2 reset 0x%llx", mss::c_str(i_target), l_data); FAPI_TRY( write_config2(i_target, l_data), "%s failed to reset wc_config2 register via write", mss::c_str(i_target) ); |
