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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-09-27 17:26:48 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-02 10:42:00 -0400 |
| commit | 7fa961df6429fdb739e29230385b7317ddc5d531 (patch) | |
| tree | a99cf24767525aa07d2cbb09221ec484bd3a64a8 /src/import/chips/p9/procedures/hwp/memory/lib/phy | |
| parent | e2305fe4b76ef9d68df9181737ebab94bd189b9a (diff) | |
| download | talos-hostboot-7fa961df6429fdb739e29230385b7317ddc5d531.tar.gz talos-hostboot-7fa961df6429fdb739e29230385b7317ddc5d531.zip | |
Fix sim problems on awan
Increase CCS polling limit for draminit training by factor of 2
Add sim check around CKE controls in RCW settings (till resolved)
Change-Id: I605bdd5355f33a39988b9c5530506bafca7e6d33
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46835
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47037
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 315e80144..45e36dd95 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -1101,7 +1101,7 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& } FAPI_INF("cal_config for %s: 0x%04lx (steps: 0x%08x)", - mss::c_str(i_target), uint16_t(l_cal_config), uint32_t(i_cal_steps_enabled)); + mss::c_str(i_target), uint16_t(l_cal_config), i_cal_steps_enabled); FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, l_cal_config) ); // Sets up the workarounds @@ -1157,7 +1157,11 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<fapi2::TARGET_TY fapi2::Assert(false); } - FAPI_DBG("executing training CCS instruction: 0x%llx, 0x%llx", l_cal_inst.arr0, l_cal_inst.arr1); + FAPI_DBG("%s executing training CCS instruction: 0x%llx, 0x%llx for cal steps 0x%08x", + mss::c_str(i_target), + l_cal_inst.arr0, + l_cal_inst.arr1, + i_cal_steps_enabled); // Delays in the CCS instruction ARR1 for training are supposed to be 0xFFFF, // and we're supposed to poll for the done or timeout bit. But we don't want @@ -1182,8 +1186,8 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<fapi2::TARGET_TY // If we got a cal timeout, or another CCS error just leave now. If we got success, check the error // bits for a cal failure. We'll return the proper ReturnCode so all we need to do is FAPI_TRY. - FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "%s failed to execute CCS program for cal steps 0x%04lx", - mss::c_str(i_target), uint16_t(i_cal_steps_enabled) ); + FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "%s failed to execute CCS program for cal steps 0x%08x", + mss::c_str(i_target), i_cal_steps_enabled ); fapi_try_exit: return fapi2::current_err; |
