Increment red_waterfall for low vdn fix

Change-Id: Iaa5dbf94fe223cdfef7ebbfe8598f98f5472c956
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46420
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46455
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>

2 files changed, 72 insertions, 6 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 05286dcfa..86a8621fa 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -1284,8 +1284,8 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
                  "%s Failed to run dqs align workaround on rp %d", mss::c_str(i_target), i_rp);
     }
 
-    // Run cal steps between RDCLK_ALIGN and RD_CTR if any are selected - note RDCLK_ALIGN takes place after WR_LEVEL
-    if (i_cal_steps_enabled.getBit<mss::cal_steps::RDCLK_ALIGN, mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN>())
+    // Run cal step READ CLOCK ALIGN
+    if (i_cal_steps_enabled.getBit<mss::cal_steps::RDCLK_ALIGN>())
     {
         // Turn off refresh
         FAPI_TRY( mss::workarounds::dqs_align::turn_off_refresh(i_target) );
@@ -1293,11 +1293,35 @@ fapi2::ReturnCode setup_and_execute_cal( const fapi2::Target<fapi2::TARGET_TYPE_
         // Sets up the cal steps in the buffer
         fapi2::buffer<uint32_t> l_steps_to_execute;
 
-        i_cal_steps_enabled.extract<mss::cal_steps::RDCLK_ALIGN,
-                                    mss::cal_steps::RDCLK_ALIGN_TO_RD_CTR_LEN,
-                                    mss::cal_steps::RDCLK_ALIGN>(l_steps_to_execute);
+        l_steps_to_execute.setBit<mss::cal_steps::RDCLK_ALIGN>();
 
-        FAPI_INF("%s Running rd_clk align through read centering vref on RP%d 0x%08x", mss::c_str(i_target), i_rp,
+        FAPI_INF("%s Running rd_clk align on RP%d 0x%08x", mss::c_str(i_target), i_rp,
+                 l_steps_to_execute);
+
+        // Undertake the calibration steps
+        FAPI_TRY( execute_cal_steps_helper(i_target, i_rp, l_steps_to_execute, i_abort_on_error) );
+
+        // Run the red_waterfall workaround for low VDN sensitivity
+        // Increments the waterfall forward by one
+        FAPI_TRY( mss::workarounds::dp16::fix_red_waterfall_gate( i_target, i_rp) );
+
+        // Turn refresh back on
+        FAPI_TRY( mss::workarounds::dqs_align::turn_on_refresh(i_target) );
+    }
+
+    if(i_cal_steps_enabled.getBit<mss::cal_steps::READ_CTR_2D_VREF, mss::cal_steps::READ_VREF_TO_READ_CTR_LEN>())
+    {
+        // Turn off refresh
+        FAPI_TRY( mss::workarounds::dqs_align::turn_off_refresh(i_target) );
+
+        // Sets up the cal steps in the buffer
+        fapi2::buffer<uint32_t> l_steps_to_execute;
+
+        l_steps_to_execute.writeBit<mss::cal_steps::READ_CTR_2D_VREF>
+        (i_cal_steps_enabled.getBit<mss::cal_steps::READ_CTR_2D_VREF>());
+        l_steps_to_execute.writeBit<mss::cal_steps::READ_CTR>(i_cal_steps_enabled.getBit<mss::cal_steps::READ_CTR>());
+
+        FAPI_INF("%s Running read centering vref through read centering on RP%d 0x%08x", mss::c_str(i_target), i_rp,
                  l_steps_to_execute);
 
         // Undertake the calibration steps
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
index 7f79078d3..322310162 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H
@@ -223,6 +223,14 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA>
             MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3,
         };
 
+        constexpr static const uint64_t RED_WATERFALL_BIT_POS[NUM_QUAD_PER_DP16] =
+        {
+            MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0,
+            MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1,
+            MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2,
+            MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3,
+        };
+
         // READ_DELAY registers, indexed by rank_pair
         static const std::vector< std::vector< uint64_t > > READ_DELAY_REG;
 
@@ -2071,6 +2079,24 @@ inline uint64_t get_blue_waterfall( const fapi2::buffer<uint64_t>& i_data )
 }
 
 ///
+/// @brief Get the red waterfall for the given quad
+/// @tparam uint64_t QUAD - which quad to access
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in] i_data the value of the register
+/// @return value of the red waterfall
+///
+template< uint64_t QUAD, fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
+inline uint64_t get_red_waterfall( const fapi2::buffer<uint64_t>& i_data )
+{
+
+    static_assert(QUAD < TT::NUM_QUAD_PER_DP16, "Inserted quad value is not less than the maximum value");
+    uint64_t l_waterfall = 0;
+    i_data.extractToRight<TT::RED_WATERFALL_BIT_POS[QUAD], TT::WATERFALL_LEN>(l_waterfall);
+    return l_waterfall;
+}
+
+///
 /// @brief Get the gate delay for the given quad
 /// @tparam uint64_t QUAD - which quad to access
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
@@ -2105,6 +2131,22 @@ inline void set_blue_waterfall( fapi2::buffer<uint64_t>& io_data, const uint64_t
 }
 
 ///
+/// @brief Set the red waterfall for the given quad
+/// @tparam uint64_t QUAD - which quad to access
+/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA
+/// @tparam TT traits type defaults to dp16Traits<T>
+/// @param[in,out] io_data the value of the register
+/// @param[in] value of the red waterfall
+///
+template< uint64_t QUAD, fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> >
+inline void set_red_waterfall( fapi2::buffer<uint64_t>& io_data, const uint64_t i_waterfall )
+{
+
+    static_assert(QUAD < TT::NUM_QUAD_PER_DP16, "QUAD value is not less than the maximum value");
+    io_data.insertFromRight<TT::RED_WATERFALL_BIT_POS[QUAD], TT::WATERFALL_LEN>(i_waterfall);
+}
+
+///
 /// @brief Set the gate delay for the given quad
 /// @tparam uint64_t QUAD - which quad to access
 /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA