L3 work for mss xmls

mss_spd, mss_volt, mss_general, mss_data_buffer, mss_update_errors

Change-Id: I1252d6d11900e88e0842c234c5ed815063e68ec0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42962
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44229
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>

3 files changed, 18 insertions, 19 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 5755589ac..3d19b1764 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -261,7 +261,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR
     // From the DDR PHY workbook
     constexpr uint64_t CONTINUOUS_UPDATE = 0x8024;
 
-    FAPI_INF("continuous update: 0x%x", CONTINUOUS_UPDATE);
+    FAPI_INF("%s continuous update: 0x%x", mss::c_str(i_target), CONTINUOUS_UPDATE);
 
     constexpr uint64_t SIM_OVERRIDE = 0x8080;
     constexpr uint64_t PHASE_CNTL_EN = 0x8020;
@@ -302,7 +302,7 @@ fapi2::ReturnCode setup_phase_rotator_control_registers( const fapi2::Target<TAR
     // All the MCA (and both registers) will be in the same state, so we can get the first and use it to create the
     // values for the others.
 
-    FAPI_INF("Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", l_update);
+    FAPI_INF("%s Write 0x%lx into the ADR SysClk Phase Rotator Control Regs", mss::c_str(i_target), l_update);
 
     // WRCLK Phase rotators are taken care of in the phy initfile. BRS 6/16.
 
@@ -1482,7 +1482,7 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET
     FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) );
     FAPI_ASSERT( !l_ranks.empty(),
                  fapi2::MSS_NO_RANKS_IN_RANK_PAIR()
-                 .set_TARGET(i_target)
+                 .set_MCA_TARGET(i_target)
                  .set_RANK_PAIR(i_rp),
                  "No ranks configured in MCA %s, rank pair %d",
                  mss::c_str(i_target),
@@ -1541,7 +1541,7 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARG
     FAPI_TRY( mss::rank::get_ranks_in_pair(i_target, i_rp, l_ranks) );
     FAPI_ASSERT( !l_ranks.empty(),
                  fapi2::MSS_NO_RANKS_IN_RANK_PAIR()
-                 .set_TARGET(i_target)
+                 .set_MCA_TARGET(i_target)
                  .set_RANK_PAIR(i_rp),
                  "No ranks configured in MCA %s, rank pair %d", mss::c_str(i_target), i_rp );
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index c20cac543..d9a7fb8e4 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -2774,7 +2774,7 @@ fapi2::ReturnCode process_rdvref_cal_errors( const fapi2::Target<fapi2::TARGET_T
         // the errors and the disables there.
         FAPI_ASSERT_NOEXIT(v == 0,
                            fapi2::MSS_FAILED_RDVREF_CAL()
-                           .set_DIMM_TARGET(i_target)
+                           .set_MCA_TARGET(i_target)
                            .set_REGISTER(TT::RD_VREF_CAL_ERROR_REG[l_index])
                            .set_VALUE(v),
                            "DP16 failed read vref calibration on %s. register 0x%016lx value 0x%016lx",
@@ -2836,7 +2836,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T
             // Now does bitwise anding to determine what's an actual error w/ the masking
             FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->first),
                                fapi2::MSS_FAILED_WRVREF_CAL()
-                               .set_DIMM_TARGET(i_target)
+                               .set_MCA_TARGET(i_target)
                                .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].first)
                                .set_VALUE(l_data_it->first)
                                .set_MASK(l_mask_it->first),
@@ -2849,7 +2849,7 @@ fapi2::ReturnCode process_wrvref_cal_errors( const fapi2::Target<fapi2::TARGET_T
 
             FAPI_ASSERT_NOEXIT(0 == (l_mask_compare & l_data_it->second),
                                fapi2::MSS_FAILED_WRVREF_CAL()
-                               .set_DIMM_TARGET(i_target)
+                               .set_MCA_TARGET(i_target)
                                .set_REGISTER(TT::WR_VREF_ERROR_REG[l_index].second)
                                .set_VALUE(l_data_it->second)
                                .set_MASK(l_mask_it->second),
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
index d97e6cc4b..8674997fd 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
@@ -154,18 +154,17 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     l_type_index = l_dimm_type[0] | l_dimm_type[1];
     l_gen_index = l_dram_gen[0] | l_dram_gen[1];
 
-    // These two checks should never be called, but better safe than seg fault
-    FAPI_ASSERT( l_type_index < NUM_DIMM_TYPES,
-                 fapi2::MSS_INVALID_DIMM_TYPE()
-                 .set_DIMM_TYPE(l_type_index)
-                 .set_TARGET(i_target),
-                 "Invalid DIMM configuration or DIMM type on %s",
-                 mss::c_str(i_target));
-    FAPI_ASSERT( l_gen_index < NUM_DIMM_GEN,
-                 fapi2::MSS_PLUG_RULES_INVALID_DRAM_GEN()
-                 .set_DRAM_GEN(l_gen_index)
-                 .set_DIMM_TARGET(i_target),
-                 "Invalid DIMM configuration or DRAM gen on %s",
+    // This check should never be called, but better safe than seg fault
+    FAPI_ASSERT( (l_type_index < NUM_DIMM_TYPES) && (l_gen_index < NUM_DIMM_GEN),
+                 fapi2::MSS_PLUG_RULES_ERROR_IN_PHY()
+                 .set_DIMM_TYPE_DIMM_0(l_dimm_type[0])
+                 .set_DIMM_TYPE_DIMM_1(l_dimm_type[1])
+                 .set_DRAM_GEN_DIMM_0(l_dram_gen[0])
+                 .set_DRAM_GEN_DIMM_1(l_dram_gen[1])
+                 .set_MCA_TARGET(i_target),
+                 "Invalid DIMM configuration or DIMM type (%d) or DRAM_GEN (%d) on %s",
+                 l_type_index,
+                 l_gen_index,
                  mss::c_str(i_target));
 
     // FOR NIMBUS PHY (as the protocol choice above is) BRS