diff options
author | Stephen Glancy <sglancy@us.ibm.com> | 2017-02-06 13:47:15 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-02-10 22:02:27 -0500 |
commit | 72f2e5f8c42cf80fdea34bc4d6e0e29abd2ab1c4 (patch) | |
tree | e93f4e10a8ffa50a62b5fad7d106963ec2a55de3 /src/import/chips/p9/procedures/hwp/memory/lib/mcbist | |
parent | 10c47be7297367f6e191dd043915b6e350a39fc8 (diff) | |
download | talos-hostboot-72f2e5f8c42cf80fdea34bc4d6e0e29abd2ab1c4.tar.gz talos-hostboot-72f2e5f8c42cf80fdea34bc4d6e0e29abd2ab1c4.zip |
Updates MCBIST for dual-drop systems
Includes:
1) address configuration updates
2) FIFO/reorder queue updates needed to avoid hangs
Change-Id: Ib5ebbe6166535ebfb4477d2e917cf5a8b057d742
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35984
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35985
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mcbist')
3 files changed, 53 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C index 38c3c6676..5c7e847a7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C @@ -437,6 +437,9 @@ fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, FAPI_TRY( clear_errors(i_target) ); + // Configures the write/read FIFO bit + FAPI_TRY( load_fifo_mode( i_target, i_program) ); + // Slam the address generator config FAPI_TRY( load_addr_gen(i_target, i_program) ); @@ -631,7 +634,7 @@ fapi_try_exit: return fapi2::current_err; } -} // namespace +} // namespace MCBIST // Note: outside of the mcbist namespace diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H index e23848566..d548951d8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H @@ -48,6 +48,7 @@ #include <lib/utils/num.H> #include <lib/mcbist/patterns.H> #include <lib/mcbist/settings.H> +#include <lib/mc/port.H> namespace mss { @@ -1020,6 +1021,7 @@ class program iv_config(0), iv_control(0), iv_async(false), + iv_fifo_mode(true), iv_pattern(PATTERN_0), iv_random24_data_seed(RANDOM24_SEEDS_0), iv_random24_seed_map(RANDOM24_SEED_MAP_0), @@ -2023,6 +2025,18 @@ class program } /// + /// @brief Enable or disable FIFO mode + /// @param[in] i_program the program in question + /// @param[in] i_mode mss::ON to enable, programs will run in FIFO vs mainline mode + /// @return void + /// + inline void change_fifo_mode( const bool i_mode ) + { + iv_fifo_mode = i_mode; + return; + } + + /// /// @brief Select the port(s) to be used by the MCBIST /// @param[in] i_ports uint64_t representing the ports. Multiple bits set imply broadcast /// i_ports is a right-aligned uint64_t, of which only the right-most 4 bits are used. The register @@ -2185,6 +2199,7 @@ class program l_equal &= iv_config == i_rhs.iv_config; l_equal &= iv_control == i_rhs.iv_control; l_equal &= iv_async == i_rhs.iv_async; + l_equal &= iv_fifo_mode == i_rhs.iv_fifo_mode; l_equal &= iv_pattern == i_rhs.iv_pattern; l_equal &= iv_thresholds == i_rhs.iv_thresholds; l_equal &= iv_data_rotate_cnfg == i_rhs.iv_data_rotate_cnfg; @@ -2244,6 +2259,9 @@ class program // True iff we want to run in asynchronous mode bool iv_async; + // True if we want to run in FIFO mode - defaults to true as this is needed for most MCBIST tests + bool iv_fifo_mode; + // The pattern for the pattern generator uint64_t iv_pattern; @@ -2818,6 +2836,33 @@ inline fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<T>& i_target, } /// +/// @brief Loads the FIFO value if needed +/// @tparam T, the fapi2::TargetType - derived +/// @tparam TT, the mcbistTraits associated with T - derived +/// @param[in] i_target the target to effect +/// @param[in] i_program the mcbist::program +/// @return FAPI2_RC_SUCCSS iff ok +/// +template< fapi2::TargetType T, typename TT = mcbistTraits<T> > +inline fapi2::ReturnCode load_fifo_mode( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) +{ + // if the FIFO load is not needed, just exit out + if(!i_program.iv_fifo_mode) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + // Turns on FIFO mode + constexpr mss::states FIFO_ON = mss::states::ON; + + FAPI_TRY(mss::configure_wrq(i_target, FIFO_ON)); + FAPI_TRY(mss::configure_rrq(i_target, FIFO_ON)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Load MCBIST data patterns and configuration /// @tparam T, the fapi2::TargetType - derived /// @tparam TT, the mcbistTraits associated with T - derived diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H index 7dec5601a..c60d4a397 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -108,6 +108,9 @@ class operation iv_const(i_const) { FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), iv_is_sim) ); + + // Disables FIFO mode, so memdiags will run in mainline mode + iv_program.change_fifo_mode(false); return; fapi_try_exit: |