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| author | Louis Stermole <stermole@us.ibm.com> | 2019-05-31 15:58:41 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-11 12:40:03 -0500 |
| commit | d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b (patch) | |
| tree | 37a342e97ffb820327dd7c64471413732e19d5ce /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | f702a3b2f6b688707968c25e44a9ae12381874c5 (diff) | |
| download | talos-hostboot-d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b.tar.gz talos-hostboot-d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b.zip | |
Add reset of FORCE_STR to exp_draminit_mc
Along with the corresponding update in exp_scominit, allows for
the PHY to perform a read latency training step to assist with
latency characterization and optimization.
JIRA EDBC-439
Change-Id: Ie12d785b9f9f7739e1435e9875797d237cbf6f1c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78190
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78206
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index aeddf0277..e2fc56ca7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -818,6 +818,23 @@ template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ); +/// +/// @brief Change the state of the force_str bit - mc_type::NIMBUS specialization +/// @tparam MC the memory controller type +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note This bit doesn't exist on Nimbus, so this is a no-op +/// +template<> +inline fapi2::ReturnCode change_force_str<DEFAULT_MC_TYPE>( + const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const states i_state ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + + // // We expect to come in to draminit with the following setup: // 1. ENABLE_RESET_N (FARB5Q(6)) 0 |
