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| author | Andre Marin <aamarin@us.ibm.com> | 2017-10-04 10:39:39 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-01 15:39:24 -0400 |
| commit | aa313fb234e1d00c425e2df84b59725f318d6548 (patch) | |
| tree | 9af01759b9ea0a8ba66654248ea5a3966e80d0c7 /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | 6b9bc4190d6086ec1384105e5579a09e1096e6c2 (diff) | |
| download | talos-hostboot-aa313fb234e1d00c425e2df84b59725f318d6548.tar.gz talos-hostboot-aa313fb234e1d00c425e2df84b59725f318d6548.zip | |
Update HPW Level for MSS API library
Change-Id: I33f36a6cc647d66c39ac46ba2922dcd1c49d86b5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47150
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47165
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
5 files changed, 10 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C index 822acde60..ef9933edb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C @@ -27,10 +27,10 @@ /// @file perf_reg.C /// @brief Subroutines to manipulate the memory controller performance registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 413271041..4fec3a846 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -27,10 +27,10 @@ /// @file port.C /// @brief Subroutines to manipulate ports (phy + mc for certain operations) /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index b6c2ece01..e7da45e66 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -27,10 +27,10 @@ /// @file port.H /// @brief Code to support ports (phy _ mc for certain operations) /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_PORT_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index bdee48e3c..5d8486f3d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -27,10 +27,10 @@ /// @file xlate.C /// @brief Subroutines to manipulate the memory controller translation registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: FSP:HB #include <fapi2.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H index 88019d483..7b745da9a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H @@ -27,10 +27,10 @@ /// @file xmalte.H /// @brief Definitions for translation registers /// -// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB:FSP #ifndef _MSS_XLT_H_ |
