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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-06-29 11:12:59 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-03 16:03:08 -0500 |
| commit | db1d65411a3dbda5fb576f74d6f318eaf8daa5cc (patch) | |
| tree | ccda7220187c277c4a5a3077252d696bf3645e32 /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | ba95d9a7d024d4238bd93a2b714f2731635e243e (diff) | |
| download | talos-hostboot-db1d65411a3dbda5fb576f74d6f318eaf8daa5cc.tar.gz talos-hostboot-db1d65411a3dbda5fb576f74d6f318eaf8daa5cc.zip | |
Implementing thermal_init
Change-Id: I7691b0f10bdcacc6be28947a8359d4d7582458c0
Original-Change-Id: I0fc6f6ab6f209f7399d0f5369b03a4504838a026
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26739
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37396
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index daf4eca7f..94a966397 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -53,20 +53,20 @@ using fapi2::TARGET_TYPE_DIMM; using fapi2::FAPI2_RC_SUCCESS; - namespace mss { +namespace mc +{ + -/// /// @brief Perform initializations of the MC translation -/// @tparm P, the fapi2::TargetType of the port -/// @tparm TT, the typename of the traits +/// @tparm P the fapi2::TargetType of the port +/// @tparm TT the typename of the traits /// @param[in] i_target, the target which has the MCA to map /// @return FAPI2_RC_SUCCESS iff ok -/// -template<> + template<> -fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGET_TYPE_MCA>& i_target) +fapi2::ReturnCode setup_xlate_map(const fapi2::Target<TARGET_TYPE_MCA>& i_target) { fapi2::buffer<uint64_t> l_xlate; fapi2::buffer<uint64_t> l_xlate1; @@ -175,7 +175,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE // Row 16,17 bit maps are ignored. // Row 15 maps to Port Address bit 6 - // Drop down the column assignments l_xlate1.insertFromRight<MCS_PORT02_MCP0XLT1_COL4_BIT_MAP, MCS_PORT02_MCP0XLT1_COL4_BIT_MAP_LEN>(0b01101); @@ -218,6 +217,5 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE fapi_try_exit: return fapi2::current_err; } - - -} // namespace +} // namespace mc +} // namespace mss |
