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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-03-07 11:43:00 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-10 17:30:25 -0500 |
| commit | 83bbce773e36e1d460d1324668c9de81c6a808ac (patch) | |
| tree | f924a37501e95926f49ba3cc6a4abffa616fb004 /src/import/chips/p9/procedures/hwp/memory/lib/mc | |
| parent | a16cab5d013872f1f330b783811e83b173e08fa2 (diff) | |
| download | talos-hostboot-83bbce773e36e1d460d1324668c9de81c6a808ac.tar.gz talos-hostboot-83bbce773e36e1d460d1324668c9de81c6a808ac.zip | |
Change accesses to IS_SIM to use mss accessor
Change-Id: Iafcaddbca510c29fb4a0289490b90b539dde2b13
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37610
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37658
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 190983f1e..e99b252a9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -462,7 +462,7 @@ template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_data; - uint8_t is_sim = 0; + uint8_t l_sim = 0; FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); @@ -475,8 +475,8 @@ fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) ); - l_data.insertFromRight<MCA_RECR_MBSECCQ_DATA_INVERSION, MCA_RECR_MBSECCQ_DATA_INVERSION_LEN>(is_sim ? 0b00 : 0b11); + FAPI_TRY( mss::is_simulation(l_sim) ); + l_data.insertFromRight<MCA_RECR_MBSECCQ_DATA_INVERSION, MCA_RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11); // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. |
