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author | Brian Silver <bsilver@us.ibm.com> | 2017-01-20 09:53:24 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-02-07 17:07:32 -0500 |
commit | e3f7d637814b291cf2f95297ba18f947b45f6dc9 (patch) | |
tree | 16f958d72485b5235e60006e8458631228456f83 /src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C | |
parent | d54d2c207077cde9a5f8ea6ac2e3afd30ddc9075 (diff) | |
download | talos-hostboot-e3f7d637814b291cf2f95297ba18f947b45f6dc9.tar.gz talos-hostboot-e3f7d637814b291cf2f95297ba18f947b45f6dc9.zip |
Map from Centaur canonical rank numbering to Nimbus
Reassigned rank pairs to be DIMM0 ranks first
ZCAL config
ODT values from VPD
Change-Id: If24e74e9e878c24125540e324cad40a7218c59ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35162
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35164
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 942e2c8a5..979ca5eb8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -35,7 +35,6 @@ #include <fapi2.H> #include <lib/mc/port.H> -#include <lib/dimm/rank.H> #include <lib/shared/mss_const.H> #include <lib/utils/scom.H> @@ -80,14 +79,13 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC fapi2::buffer<uint16_t> l_per_zqcal_mode_options = 0; fapi2::buffer<uint64_t> l_periodic_cal_config; - fapi2::buffer<uint64_t> l_phy_zqcal_config; std::vector<uint64_t> l_pairs; FAPI_INF("Enable periodic cal"); uint8_t is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), is_sim) ); + FAPI_TRY( mss::is_simulation(is_sim) ); // Even if we're in sim, do these so that we do the attribute work (even though the values aren't used.) FAPI_TRY( mss::eff_memcal_interval(i_target, l_memcal_interval) ); @@ -128,8 +126,6 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // ZQCAL if (l_per_zqcal_mode_options != 0) { - std::vector<uint64_t> l_ranks; - // // Configure the controller // @@ -162,20 +158,11 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // // Setup PER_ZCAL_CONFIG based on the number of ranks on the DIMM in either slot. - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - for (auto r : l_ranks) - { - l_phy_zqcal_config.setBit(TT::PER_ZCAL_ENA_RANK + r); - } + FAPI_TRY( reset_zqcal_config(i_target) ); // No ZQCAL in sim l_periodic_cal_config.writeBit<TT::PER_ENA_ZCAL>(is_sim ? 0 : 1); - // Write the ZQCAL periodic config - FAPI_INF("zcal periodic config: 0x%016lx", l_phy_zqcal_config); - FAPI_TRY( mss::putScom(i_target, TT::PHY_ZQCAL_REG, l_phy_zqcal_config) ); - // Write the ZQCAL timer reload register // # DPHY01_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 0x00A 0x8000c0090301143f // # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG09_L2 @@ -210,7 +197,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC FAPI_TRY( mss::rank::get_rank_pairs(i_target, l_pairs) ); - for (auto pair : l_pairs) + for (const auto pair : l_pairs) { l_rank_config.setBit(pair); } |