L3 support for ddr_phy_reset, termination_control

Change-Id: I70ad1f23dabc4b9f169821b30a903a200f52fbc4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42437
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42452
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>

13 files changed, 21 insertions, 33 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
index 963c06ced..60e39e58b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H
@@ -28,7 +28,7 @@
 /// @brief Run and manage the DDR4 control words for the RCD and data buffers
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
 // *HWP Consumed by: FSP:HB
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
index c6dc9c2d2..694831f42 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
@@ -28,7 +28,7 @@
 /// @brief Code to support data_buffer_ddr4
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
 // *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
index d9e553cd5..cc96e9253 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C
@@ -28,7 +28,7 @@
 /// @brief Latches WR VREF according to JEDEC spec
 ///
 // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 2
 // *HWP Consumed by: FSP:HB Memory
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
index fffa45832..6c95f1280 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H
@@ -28,7 +28,7 @@
 /// @brief Latches WR VREF according to JEDEC spec
 ///
 // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 2
 // *HWP Consumed by: FSP:HB Memory
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
index 1fcbe1b79..b1f181469 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,10 @@
 /// @file mrs00.C
 /// @brief Run and manage the DDR4 MRS00 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
-// *HWP Level: 1
+// *HWP Level: 3
 // *HWP Consumed by: FSP:HB
 
 #include <fapi2.H>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
index 19e4c71a1..b7cfcd4fb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
@@ -27,7 +27,7 @@
 /// @file mrs01.C
 /// @brief Run and manage the DDR4 MRS01 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
index 1c86e63e5..7119c0240 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C
@@ -27,7 +27,7 @@
 /// @file mrs02.C
 /// @brief Run and manage the DDR4 MRS02 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
index a24421be3..922665c36 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C
@@ -27,7 +27,7 @@
 /// @file mrs03.C
 /// @brief Run and manage the DDR4 DDR4 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
index 23831968a..9be19ebfd 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C
@@ -27,7 +27,7 @@
 /// @file mrs05.C
 /// @brief Run and manage the DDR4 MRS05 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
index 3064909f3..104657819 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C
@@ -27,7 +27,7 @@
 /// @file mrs06.C
 /// @brief Run and manage the DDR4 MRS06 loading
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
index 98ddc889c..92e576610 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H
@@ -27,7 +27,7 @@
 /// @file mrs_load_ddr4.H
 /// @brief Code to support mrs_load_ddr4
 ///
-// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 1
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H
index a3a18b01a..7cf49f8e2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/state_machine.H
@@ -28,7 +28,7 @@
 /// @brief state_machine delcaration
 ///
 // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
-// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
+// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com>
 // *HWP Team: Memory
 // *HWP Level: 2
 // *HWP Consumed by: HB:FSP
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H
index bdd0a7a3d..8c214acc1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H
@@ -70,20 +70,6 @@ enum
 };
 
 ///
-/// @brief set of enums used for ffdc return codes
-///
-enum rank_functions
-{
-    RANK_PAIR_TO_PHY = 0,
-    RANK_PAIR_FROM_PHY = 1,
-    SET_RANKS_IN_PAIR = 2,
-    GET_RANKS_IN_PAIR = 3,
-    GET_RANK_FIELD = 4,
-    GET_PAIR_VALID = 5,
-    SET_RANK_FIELD = 6,
-    RD_CTR_WORKAROUND_READ_DATA = 7,
-};
-///
 /// @class rankPairTraits
 /// @brief a collection of traits associated with rank pairs
 /// @tparam T fapi2::TargetType representing the PHY
@@ -1193,6 +1179,8 @@ template< uint64_t RP, fapi2::TargetType T, typename TT = rankPairTraits<T, RP>
 fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target,
                                      std::vector<uint64_t>& o_ranks )
 {
+    static_assert(RP < MAX_RANK_PER_DIMM, "Passed in Rank Pair is too high");
+
     o_ranks.clear();
 
     // Read the rank pair register(s)
@@ -1338,12 +1326,12 @@ inline fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target,
             FAPI_ASSERT( false,
                          fapi2::MSS_INVALID_RANK_PAIR()
                          .set_RANK_PAIR(i_rp)
-                         .set_MCA_TARGET(i_target)
-                         .set_FUNCTION(GET_RANKS_IN_PAIR),
-                         "%s Invalid rank pair (%d) in get_ranks_in_pair",
+                         .set_FUNCTION(GET_RANKS_IN_PAIR)
+                         .set_MCA_TARGET(i_target),
+                         "%s Invalid number of rankpairs entered. num: %lu max: %lu",
                          mss::c_str(i_target),
-                         i_rp);
-
+                         i_rp,
+                         MAX_PRIMARY_RANKS_PER_PORT);
             break;
     }