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| author | Chris Steffen <cwsteffen@us.ibm.com> | 2017-07-11 15:58:06 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-07-31 14:36:19 -0400 |
| commit | ab0c2a4ed75a1d779adf4195961be1b3abb84a56 (patch) | |
| tree | f0156a7c2d1cd05b11dd96066d16a950b1b7e6da /src/import/chips/p9/procedures/hwp/io | |
| parent | 7afc961159aa0cdb6f0a052d188b9af7081db83a (diff) | |
| download | talos-hostboot-ab0c2a4ed75a1d779adf4195961be1b3abb84a56.tar.gz talos-hostboot-ab0c2a4ed75a1d779adf4195961be1b3abb84a56.zip | |
Obus I/O Image Build Fix
- Updated Scom Address
- Added Makefile for wrapper
Change-Id: I48d977042b6d3011051aa0da2e462b0c41ec353a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43006
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gary A. Peterson <garyp@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43007
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/io')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/io/p9_io_obus_image_build.C | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_image_build.C b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_image_build.C index 5183eafdb..339f85c4e 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_obus_image_build.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_obus_image_build.C @@ -93,7 +93,7 @@ fapi2::ReturnCode p9_io_obus_image_build(CONST_OBUS& iTgt, void* const iHwImageP const uint64_t HARD_RESET = 0x6000000000000000ull; // xcr cmd=110 const uint64_t RESUME_FROM_HALT = 0x2000000000000000ull; // xcr cmd=010 // PPE Address - const uint64_t BASE_ADDR = 0x0000000006010C00ull; + const uint64_t BASE_ADDR = 0x0000000009011040ull; const uint64_t MEM_ARB_CSAR = 0x000000000000000Dull | BASE_ADDR; // Sram Address Reg const uint64_t MEM_ARB_SCR = 0x000000000000000Aull | BASE_ADDR; // Sram Source Control Reg const uint64_t MEM_ARB_CSDR = 0x000000000000000Eull | BASE_ADDR; // Sram Data Reg |
