Cache/Core stop clocks: add shut down of Power Management to remove contentions

Ported changes from https://ralgit01.raleigh.ibm.com/gerrit1/#/c/44781/25 to
simplify auto mirror conflicts and reuse existing SBE HWP files

- Halt SGPE, PGPE and CMEs assocatiated within the targeted EQ
- Clear the PCB atomic lock that may be in place by SGPE
- Add core stopclocks changes
- Fixed cache stop clocks XML callout
- Fix atomic lock library dependencies
- Only enable function on DD2
- Halt PPE only if not already in halt
- Enhance PPE Halt FFDC

Key_Cronus_Test=PM_REGRESS

Change-Id: Id6c11176d222213bf1a01b91cade41de989f04c6
RTC: 180317
CQ: SW406569
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50415
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50421
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 55 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
index d730e565d..4ced3eb62 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
@@ -43,7 +43,15 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_hcd_common.H>
 #include <p9_common_clk_ctrl_state.H>
-#include "p9_hcd_core_stopclocks.H"
+#include <p9_hcd_core_stopclocks.H>
+#include <p9_hcd_cache_stopclocks.H>
+#include <p9_eq_clear_atomic_lock.H>
+#ifdef __PPE__
+    #include <p9_sbe_ppe_utils.H>
+#else
+    #include <p9_ppe_utils.H>
+#endif
+#include <p9_ppe_defs.H>
 
 //------------------------------------------------------------------------------
 // Constant Definitions
@@ -82,6 +90,9 @@ p9_hcd_core_stopclocks(
     auto  l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
     auto  l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
 
+    auto l_ex_vector = l_quad.getChildren<fapi2::TARGET_TYPE_EX>
+                       (fapi2::TARGET_STATE_FUNCTIONAL);
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
                            l_attr_sdisn_setup));
 
@@ -132,8 +143,44 @@ p9_hcd_core_stopclocks(
 
         if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0)
         {
-            //halt cme(poll for halted, if timeout, print warnning keep going).
 
+#ifdef DD2
+            FAPI_DBG("Halting the PGPE ...");
+            l_rc = ppe_halt(l_chip, PGPE_BASE_ADDRESS);
+            FAPI_ASSERT_NOEXIT(!l_rc,
+                               fapi2::CORE_STOPCLKS_PGPE_HALT_TIMEOUT()
+                               .set_CHIP(l_chip),
+                               "PSTATE GPE Halt timeout");
+
+            FAPI_DBG("Halting the SGPE ...");
+            l_rc = ppe_halt(l_chip, SGPE_BASE_ADDRESS);
+            FAPI_ASSERT_NOEXIT(!l_rc,
+                               fapi2::CORE_STOPCLKS_SGPE_HALT_TIMEOUT()
+                               .set_CHIP(l_chip),
+                               "STOP GPE Halt timeout");
+
+            FAPI_DBG("Clear the atomic lock on EQ %d", l_attr_chip_unit_pos);
+            l_rc = p9_clear_atomic_lock(l_quad);
+            FAPI_ASSERT_NOEXIT(!l_rc,
+                               fapi2::CORE_STOPCLKS_ATOMIC_LOCK_FAIL()
+                               .set_EQ(l_quad),
+                               "EQ Atomic Halt timeout");
+
+            for ( auto& ex : l_ex_vector )
+            {
+                fapi2::ATTR_CHIP_UNIT_POS_Type  l_cme_id = 0;
+                FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, ex, l_cme_id));
+
+                FAPI_DBG("Halting CME %d", l_cme_id );
+                uint64_t l_cme_base_address = getCmeBaseAddress (l_cme_id);
+                l_rc = ppe_halt(l_chip, l_cme_base_address);
+                FAPI_ASSERT_NOEXIT(!l_rc,
+                                   fapi2::CACHE_STOPCLKS_CME_HALT_TIMEOUT()
+                                   .set_EX(ex),
+                                   "CME Halt timeout");
+            }
+
+#endif
             FAPI_DBG("Assert Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]");
             FAPI_TRY(putScom(l_quad,
                              (l_attr_chip_unit_pos < 2) ?
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.mk b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.mk
index 3578af488..0a0012ba0 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.mk
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.mk
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2016
+# Contributors Listed Below - COPYRIGHT 2016,2017
 # [+] International Business Machines Corp.
 #
 #
@@ -24,5 +24,9 @@
 # IBM_PROLOG_END_TAG
 PROCEDURE=p9_hcd_core_stopclocks
 $(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
-OBJS+=p9_hcd_core_stopclocks.o
+$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/cache)
+$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/ffdc)
+lib$(PROCEDURE)_DEPLIBS=p9_hcd_cache_stopclocks
+lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils
+lib$(PROCEDURE)_DEPLIBS+=p9_eq_clear_atomic_lock
 $(call BUILD_PROCEDURE)