Initial pass at adding Axone support - fix dmi PPE scom translation.

Change-Id: I930e067f97ee40f4d07e260b08076fdc323da851
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45078
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45080
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 55 insertions, 19 deletions

diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H
index 4cebaf1fb..7b90eb7bc 100644
--- a/src/import/chips/p9/common/scominfo/p9_cu.H
+++ b/src/import/chips/p9/common/scominfo/p9_cu.H
@@ -47,6 +47,7 @@ extern "C"
     {
         P9C_CHIP,            ///< Cumulus chip (included for future expansion)
         P9N_CHIP,            ///< Nimbus chip (included for future expansion)
+        P9A_CHIP,            ///< Axone chip (included for future expansion)
         PU_C_CHIPUNIT,       ///< Core
         PU_EQ_CHIPUNIT,      ///< Quad
         PU_EX_CHIPUNIT,      ///< EX
@@ -57,6 +58,7 @@ extern "C"
         PU_PHB_CHIPUNIT,     ///< PCIe (PHB)
         PU_MI_CHIPUNIT,      ///< MI (Cumulus only)
         PU_DMI_CHIPUNIT,     ///< DMI (Cumulus only)
+        PU_OMI_CHIPUNIT,     ///< OMI (Axone only)
         PU_MCS_CHIPUNIT,     ///< MCS (Nimbus only)
         PU_MCA_CHIPUNIT,     ///< MCA (Nimbus only)
         PU_MCBIST_CHIPUNIT,  ///< MCBIST (Nimbus only)
@@ -83,15 +85,16 @@ extern "C"
     };
 
     /// P9 PPE Chip Unit Instance Number enumeration
-    /// PPE name        Nimbus    Cumulus
-    /// SBE             0         0
-    /// GPE0..3         10..13    10..13
-    /// CME0            20..25    20..25
-    /// CME1            30..35    30..35
-    /// IO PPE (xbus)   40        40
-    /// IO PPE (obus)   41,42     41,42
-    /// IO PPE (dmi)    NA        43,44
-    /// Powerbus PPEs   50        50..52
+    /// PPE name        Nimbus    Cumulus   Axone
+    /// SBE             0         0         0
+    /// GPE0..3         10..13    10..13    10..13
+    /// CME0            20..25    20..25    20..25
+    /// CME1            30..35    30..35    30..35
+    /// IO PPE (xbus)   40        40        40
+    /// IO PPE (obus)   41,44     41..44    41,44
+    /// IO PPE (dmi)    NA        45,46     NA
+    /// Powerbus PPEs   50        50        50
+    /// IO PPE (omi)    NA        NA        56..61
     typedef enum
     {
         PPE_SBE_CHIPUNIT_NUM         =  0,
@@ -104,10 +107,14 @@ extern "C"
         PPE_IO_XBUS_CHIPUNIT_NUM     = 40,
         PPE_IO_OB0_CHIPUNIT_NUM      = 41,
         PPE_IO_OB1_CHIPUNIT_NUM      = 42,
-        PPE_IO1_DMI_CHIPUNIT_NUM     = 44,
+        PPE_IO_OB2_CHIPUNIT_NUM      = 43,
+        PPE_IO_OB3_CHIPUNIT_NUM      = 44,
+        PPE_IO_DMI0_CHIPUNIT_NUM     = 45,
+        PPE_IO_DMI1_CHIPUNIT_NUM     = 46,
         PPE_PB0_CHIPUNIT_NUM         = 50,
         PPE_PB2_CHIPUNIT_NUM         = 52,
-        PPE_LAST_CHIPUNIT_NUM        = PPE_PB2_CHIPUNIT_NUM,
+        PPE_OMI_CHIPUNIT_NUM         = 56,
+        PPE_LAST_CHIPUNIT_NUM        = PPE_OMI_CHIPUNIT_NUM,
     } p9_ppe_chip_unit_instance_num_t;
 
 } // extern "C"
diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
index faf6fe876..ab424fb01 100644
--- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H
+++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
@@ -305,13 +305,22 @@ extern "C"
     /// Cumulus mc rings
     typedef enum
     {
-        P9C_MC_CHAN_RING_ID = 0x2,
-        P9C_MC_IO_RING_ID   = 0x4,
-        P9C_MC_BIST_RING_ID = 0x8
+        P9C_MC_PSCM_RING_ID  = 0x0,
+        P9C_MC_PERV_RING_ID  = 0x1,
+        P9C_MC_CHAN_RING_ID  = 0x2,
+        P9C_MC_MCTRA_RING_ID = 0x3,
+        P9C_MC_IO_RING_ID    = 0x4,
+        P9C_MC_PPE_RING_ID   = 0x5,
+        P9C_MC_BIST_RING_ID  = 0x8
     } p9c_mc_ring_id_t;
 
     typedef enum
     {
+        P9C_MC_PPE_SAT_ID = 0x1
+    } p9c_mc_ppe_sat_id_t;
+
+    typedef enum
+    {
         P9C_MC_OFFSET_IND = 0x3F
     } p9c_mc_sat_offset_t;
 
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C
index 10bc2e9b9..8e4bfc90d 100644
--- a/src/import/chips/p9/common/scominfo/p9_scominfo.C
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C
@@ -470,8 +470,8 @@ extern "C"
                         l_scom.set_sat_id(PPE_CME_SAT_ID);
                     }
 
-                    // PPE IO (XBUS/OBUS/DMI)
-                    else if ( (i_chipUnitNum >= PPE_IO_XBUS_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_IO1_DMI_CHIPUNIT_NUM) )
+                    // PPE IO (XBUS/OBUS)
+                    else if ( (i_chipUnitNum >= PPE_IO_XBUS_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_IO_OB3_CHIPUNIT_NUM) )
                     {
                         l_scom.set_chiplet_id( XB_CHIPLET_ID +
                                                (i_chipUnitNum % PPE_IO_XBUS_CHIPUNIT_NUM) +
@@ -490,6 +490,15 @@ extern "C"
                         l_scom.set_sat_id(OB_PPE_SAT_ID); // Same SAT_ID value for XBUS
                     }
 
+                    // PPE IO (DMI)
+                    else if ( (i_chipUnitNum >= PPE_IO_DMI0_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_IO_DMI1_CHIPUNIT_NUM))
+                    {
+                        l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum - PPE_IO_DMI0_CHIPUNIT_NUM));
+                        l_scom.set_ring(MC_IOM01_1_RING_ID);
+                        l_scom.set_port(UNIT_PORT_ID);
+                        l_scom.set_sat_id(P9C_MC_PPE_SAT_ID);
+                    }
+
                     // PPE PB
                     else if ( (i_chipUnitNum >= PPE_PB0_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_PB2_CHIPUNIT_NUM) )
                     {
@@ -723,9 +732,10 @@ extern "C"
                             ( (l_ring == P9C_MC_BIST_RING_ID) &&
                               (l_sat_id != P9C_SAT_ID_CHAN_MCBIST)
                             ) ||
-                            ( (l_ring == MC_PERV_RING_ID) || //Translate MC perv regs with MC
-                              (l_ring == XB_PSCM_RING_ID) ||
-                              (l_ring == MC_MCTRA_0_RING_ID)
+                            ( (l_ring == P9C_MC_PERV_RING_ID) || //Translate MC perv regs with MC
+                              (l_ring == P9C_MC_PSCM_RING_ID) ||
+                              (l_ring == P9C_MC_MCTRA_RING_ID) ||
+                              (l_ring == P9C_MC_PPE_RING_ID)
                             ) ||
                             ( (l_ring == P9C_MC_IO_RING_ID) &&
                               (l_sat_id == MC_IND_SAT_ID) &&
@@ -918,8 +928,16 @@ extern "C"
                         }
                     }
 
+                    //DMI PPE Registers
+                    if ( l_ring == P9C_MC_PPE_RING_ID )
+                    {
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                                    (l_chiplet_id - MC01_CHIPLET_ID) + PPE_IO_DMI0_CHIPUNIT_NUM));
+                    }
                 }
 
+
             }
 
             // PU_NV_CHIPUNIT
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.H b/src/import/chips/p9/common/scominfo/p9_scominfo.H
index 38c74888a..f3107c606 100644
--- a/src/import/chips/p9/common/scominfo/p9_scominfo.H
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.H
@@ -50,6 +50,8 @@ extern "C"
     static const uint32_t P9N_DD2_SI_MODE = 0x2;
     static const uint32_t P9C_DD1_SI_MODE = 0x4;
     static const uint32_t P9C_DD2_SI_MODE = 0x8;
+    static const uint32_t P9A_DD1_SI_MODE = 0x10;
+    static const uint32_t P9A_DD2_SI_MODE = 0x20;
 
     typedef enum
     {