First pass updates of scominfo for Cumulus.

Change-Id: Id4d46a80959256b5dd815181e9424c3fdcc8b915
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38181
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: JOSHUA L. HANNAN <jlhannan@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38183
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 380 insertions, 70 deletions

diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H
index 15c1f803f..4cebaf1fb 100644
--- a/src/import/chips/p9/common/scominfo/p9_cu.H
+++ b/src/import/chips/p9/common/scominfo/p9_cu.H
@@ -64,6 +64,7 @@ extern "C"
         PU_PPE_CHIPUNIT,     ///< PPE
         PU_SBE_CHIPUNIT,     ///< SBE
         PU_CAPP_CHIPUNIT,    ///< CAPP
+        PU_MC_CHIPUNIT,    ///< mc
         NONE,                ///< None/Invalid
     } p9ChipUnits_t;
 
diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
index 01d6b6b0f..23d4c5f36 100644
--- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H
+++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -210,6 +210,14 @@ extern "C"
         N3_PB_5_RING_ID = 0xe,      ///< PB_5
     } p9_n3_ring_id_t;
 
+
+    /// P9 N3 satellite ids
+    typedef enum
+    {
+        P9C_N3_MCS01_SAT_ID = 0,
+        P9C_N3_MCS23_SAT_ID = 2
+    } p9_n3_sat_id_t;
+
     /// P9 XBUS chiplet SCOM ring ID enumeration
     /// source: tpc_p9_xb_top.vhdl
     typedef enum
@@ -262,7 +270,7 @@ extern "C"
         MC_DIR_SAT_ID_ECC64_0 = 0x8,
         MC_DIR_SAT_ID_ECC64_1 = 0x9,
         MC_DIR_SAT_ID_ECC64_2 = 0xa,
-        MC_DIR_SAT_ID_ECC64_3 = 0xb,
+        MC_DIR_SAT_ID_ECC64_3 = 0xb
     } p9_mc_dir0_sat_id_t;
 
     //These are for registers that reside in the MCS chiplet, but
@@ -288,13 +296,24 @@ extern "C"
 
     typedef enum
     {
-        MC_DIR_SAT_ID_MCBIST = 0xC
+        MC_IND_SAT_ID = 0x0,
+        MC_DIR_SAT_ID_MCBIST = 0xC,
+        P9C_SAT_ID_CHAN_MCBIST = 0xD
     } p9_mc_dir1_sat_id_t;
 
+
+    /// Cumulus mc rings
     typedef enum
     {
-        MC_IND_SAT_ID = 0x0
-    } p9_mc_ind_sat_id_t;
+        P9C_MC_CHAN_RING_ID = 0x2,
+        P9C_MC_IO_RING_ID   = 0x4,
+        P9C_MC_BIST_RING_ID = 0x8
+    } p9c_mc_ring_id_t;
+
+    typedef enum
+    {
+        P9C_MC_OFFSET_IND = 0x3F
+    } p9c_mc_sat_offset_t;
 
     /// P9 OB chiplet SCOM ring ID enumeration
     /// source: tpc_p9_ob_top.vhdl
@@ -368,7 +387,6 @@ extern "C"
         PPE_PB_SAT_ID = 0x0,
     } p9_n3_ppe_sat_id;
 
-
 //        8             7             6             5             4             3          2         1
 //
 //  |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31|
@@ -521,6 +539,22 @@ extern "C"
                 return;
             }
 
+            /// @brief Extract the RX or TX Group ID of an indirect scom address
+            /// @retval uint8_t Satellite register offset field value
+            inline uint8_t get_rxtx_group_id()
+            {
+                return (iv_addr >> 37) & 0x3F;
+            }
+
+            /// @brief Modify SCOM address, update the RX or TX Group ID
+            /// @param[in] i_grp_id Group id to set
+            /// @retval none
+            inline void set_rxtx_group_id(uint8_t i_grp_id)
+            {
+                iv_addr &= 0xFFFFF81FFFFFFFFFULL;
+                iv_addr |= (i_grp_id & 0x3FULL) << 37;
+            }
+
             /// @brief Determine if SCOM address is valid/well-formed
             /// @retval bool True if SCOM address is valid, false otherwise
             inline bool is_valid() const
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C
index 1a39616bc..28a44e8e3 100644
--- a/src/import/chips/p9/common/scominfo/p9_scominfo.C
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C
@@ -46,6 +46,7 @@ extern "C"
     {
         p9_scom_addr l_scom(i_scomAddr);
         uint8_t l_ring = l_scom.get_ring();
+        uint8_t l_chiplet_id = l_scom.get_chiplet_id();
 
         //Used to help generate entries for the SCOMdef documentation,
         //These aren't general PIB addresses
@@ -148,6 +149,111 @@ extern "C"
 
                     break;
 
+                case PU_MC_CHIPUNIT:
+                    l_scom.set_chiplet_id(MC01_CHIPLET_ID + i_chipUnitNum);
+                    break;
+
+                case PU_MI_CHIPUNIT:
+                    //-------------------------------------------
+                    // MI
+                    //-------------------------------------------
+                    //          Chiplet   Ring   Satid   Off
+                    //MCS0           05     02       0   !SCOM3
+                    //MCS1           05     02       2   !SCOM3
+                    //MCS2           03     02       0   !SCOM3
+                    //MCS3           03     02       2   !SCOM3
+                    l_scom.set_chiplet_id(N3_CHIPLET_ID - (2 * (i_chipUnitNum / 2)));
+                    l_scom.set_sat_id(2 * (i_chipUnitNum % 2));
+                    break;
+
+                case PU_DMI_CHIPUNIT:
+                    if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)))
+                    {
+                        //SCOM3   (See mc_clscom_rlm.fig <= 0xB vs mc_scomfir_rlm.fig > 0xB)
+                        //DMI0           05     02       0   0x2X (X <= 0xB)
+                        //DMI1           05     02       0   0x3X (X <= 0xB)
+                        //DMI2           05     02       2   0x2X (X <= 0xB)
+                        //DMI3           05     02       2   0x3X (X <= 0xB)
+                        //DMI4           03     02       0   0x2X (X <= 0xB)
+                        //DMI5           03     02       0   0x3X (X <= 0xB)
+                        //DMI6           03     02       2   0x2X (X <= 0xB)
+                        //DMI7           03     02       2   0x3X (X <= 0xB)
+                        l_scom.set_chiplet_id(N3_CHIPLET_ID - (2 * (i_chipUnitNum / 4)));
+                        l_scom.set_sat_id(2 * ((i_chipUnitNum / 2) % 2));
+                        uint8_t l_sat_offset = l_scom.get_sat_offset();
+                        l_sat_offset = (l_sat_offset & 0xF) + ((2 + (i_chipUnitNum % 2)) << 4);
+                        l_scom.set_sat_offset(l_sat_offset);
+                    }
+
+                    if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)))
+                    {
+                        //-------------------------------------------
+                        // DMI
+                        //-------------------------------------------
+                        //SCOM1,2
+                        //DMI0           07     02       0
+                        //DMI1           07     02       1
+                        //DMI2           07     02       2
+                        //DMI3           07     02       3
+                        //DMI4           08     02       0
+                        //DMI5           08     02       1
+                        //DMI6           08     02       2
+                        //DMI7           08     02       3
+                        if (l_ring == P9C_MC_CHAN_RING_ID)
+                        {
+                            l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum / 4));
+                            l_scom.set_sat_id(i_chipUnitNum % 4);
+                        }
+
+                        //SCOM4
+                        //DMI0           07     08     0xD   0x0X
+                        //DMI1           07     08     0xD   0x1X
+                        //DMI2           07     08     0xD   0x2X
+                        //DMI3           07     08     0xD   0x3X
+                        //DMI4           08     08     0xD   0x0X
+                        //DMI5           08     08     0xD   0x1X
+                        //DMI6           08     08     0xD   0x2X
+                        //DMI7           08     08     0xD   0x3X
+                        if (l_ring == P9C_MC_BIST_RING_ID)
+                        {
+                            l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum / 4));
+                            uint8_t l_sat_offset = l_scom.get_sat_offset();
+                            l_sat_offset = (l_sat_offset & 0xF) + ((i_chipUnitNum % 2) << 4);
+                            l_scom.set_sat_offset(l_sat_offset);
+                        }
+
+                        //-------------------------------------------
+                        // DMI IO
+                        //-------------------------------------------
+                        //          Chiplet   Ring   Satid    Off    RXTXGrp
+                        //DMI0           07     04       0   0x3F       0x00
+                        //DMI1           07     04       0   0x3F       0x01
+                        //DMI2           07     04       0   0x3F       0x02
+                        //DMI3           07     04       0   0x3F       0x03
+                        //DMI4           08     04       0   0x3F       0x00
+                        //DMI5           08     04       0   0x3F       0x01
+                        //DMI6           08     04       0   0x3F       0x02
+                        //DMI7           08     04       0   0x3F       0x03
+
+                        //DMI0           07     04       0   0x3F       0x20
+                        //DMI1           07     04       0   0x3F       0x21
+                        //DMI2           07     04       0   0x3F       0x22
+                        //DMI3           07     04       0   0x3F       0x23
+                        //DMI4           08     04       0   0x3F       0x20
+                        //DMI5           08     04       0   0x3F       0x21
+                        //DMI6           08     04       0   0x3F       0x22
+                        //DMI7           08     04       0   0x3F       0x23
+                        if (l_ring == P9C_MC_IO_RING_ID)
+                        {
+                            l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum / 4));
+                            uint8_t l_rxtx_grp = l_scom.get_rxtx_group_id();
+                            l_scom.set_rxtx_group_id((l_rxtx_grp & 0xF0) + (i_chipUnitNum % 4));
+                        }
+
+                    }
+
+                    break;
+
                 case PU_NV_CHIPUNIT:
                     if (i_mode == P9N_DD1_SI_MODE)
                     {
@@ -489,76 +595,245 @@ extern "C"
                                             (l_chiplet_id / 2) - 1));
             }
 
-            // PU_MCS_CHIPUNIT (nest)
-            // mcs: 0..3
-            if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
-                (l_port == UNIT_PORT_ID) &&
-                (l_ring == N3_MC01_0_RING_ID) &&
-                ((l_sat_id == MC_DIR_SAT_ID_PBI_01) || (l_sat_id == MC_DIR_SAT_ID_PBI_23)) &&
-                (((0x2F & l_sat_offset) < MC_MCS_MCA_OFFSET_MCP0XLT0 || MC_MCS_MCA_OFFSET_MCPERF3 < (0x2F & l_sat_offset))))
+            //==== NIMBUS ====
+            if (i_mode == P9N_DD1_SI_MODE || i_mode == P9N_DD2_SI_MODE)
             {
-                o_chipUnitRelated = true;
-                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCS_CHIPUNIT,
-                                            ((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2)) +
-                                            (l_sat_id / 2)));
-            }
+                // PU_MCS_CHIPUNIT (nest)
+                // mcs: 0..3
+                if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID) &&
+                    (l_ring == N3_MC01_0_RING_ID) &&
+                    ((l_sat_id == MC_DIR_SAT_ID_PBI_01) || (l_sat_id == MC_DIR_SAT_ID_PBI_23)) &&
+                    (((0x2F & l_sat_offset) < MC_MCS_MCA_OFFSET_MCP0XLT0 || MC_MCS_MCA_OFFSET_MCPERF3 < (0x2F & l_sat_offset))))
+                {
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCS_CHIPUNIT,
+                                                ((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2)) +
+                                                (l_sat_id / 2)));
+                }
 
-            // PU_MCBIST_CHIPUNIT (mc)
-            // mcbist: 0..1
-            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
-                (((l_port == UNIT_PORT_ID) &&
-                  (((l_ring == MC_MC01_1_RING_ID) &&
-                    ((l_sat_id & 0xC) == MC_DIR_SAT_ID_MCBIST)) || //MCBIST has 2 bit sat_id
-                   ((l_ring == MC_PERV_RING_ID) || //Translate MC perv regs with MCBIST
-                    (l_ring == XB_PSCM_RING_ID) ||
-                    (l_ring == MC_MCTRA_0_RING_ID)) )) || //Translate TRA regs with MCBIST
-                 (l_port != UNIT_PORT_ID)) )   //Translate MC perv regs with MCBIST
-            {
-                o_chipUnitRelated = true;
-                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCBIST_CHIPUNIT,
-                                            l_chiplet_id - MC01_CHIPLET_ID));
-            }
+                // PU_MCBIST_CHIPUNIT (mc)
+                // mcbist: 0..1
+                if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                    (((l_port == UNIT_PORT_ID) &&
+                      (((l_ring == MC_MC01_1_RING_ID) &&
+                        ((l_sat_id & 0xC) == MC_DIR_SAT_ID_MCBIST)) || //MCBIST has 2 bit sat_id
+                       ((l_ring == MC_PERV_RING_ID) || //Translate MC perv regs with MCBIST
+                        (l_ring == XB_PSCM_RING_ID) ||
+                        (l_ring == MC_MCTRA_0_RING_ID)) )) || //Translate TRA regs with MCBIST
+                     (l_port != UNIT_PORT_ID)) )   //Translate MC perv regs with MCBIST
+                {
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCBIST_CHIPUNIT,
+                                                l_chiplet_id - MC01_CHIPLET_ID));
+                }
 
-            // PU_MCA_CHIPUNIT (mc)
-            // mca: 0..7
-            // These regisers are in the mcs chiplet but are logically mca targetted
-            if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
-                (l_port == UNIT_PORT_ID) &&
-                (l_ring == N3_MC01_0_RING_ID) &&
-                ((l_sat_id == MC_DIR_SAT_ID_PBI_01) || (l_sat_id == MC_DIR_SAT_ID_PBI_23)) &&
-                (((0x2F & l_sat_offset) >= MC_MCS_MCA_OFFSET_MCP0XLT0 && MC_MCS_MCA_OFFSET_MCPERF3 >= (0x2F & l_sat_offset))))
-            {
-                o_chipUnitRelated = true;
-                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
-                                            ((((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2)) +
-                                              (l_sat_id / 2)) * 2) +
-                                            ((l_sat_offset & 0x10) >> 4) ));
-            }
+                // PU_MCA_CHIPUNIT (mc)
+                // mca: 0..7
+                // These regisers are in the mcs chiplet but are logically mca targetted
+                if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID) &&
+                    (l_ring == N3_MC01_0_RING_ID) &&
+                    ((l_sat_id == MC_DIR_SAT_ID_PBI_01) || (l_sat_id == MC_DIR_SAT_ID_PBI_23)) &&
+                    (((0x2F & l_sat_offset) >= MC_MCS_MCA_OFFSET_MCP0XLT0 && MC_MCS_MCA_OFFSET_MCPERF3 >= (0x2F & l_sat_offset))))
+                {
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
+                                                ((((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2)) +
+                                                  (l_sat_id / 2)) * 2) +
+                                                ((l_sat_offset & 0x10) >> 4) ));
+                }
 
-            // PU_MCA_CHIPUNIT (mc)
-            // mca: 0..7
-            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
-                (l_port == UNIT_PORT_ID) &&
-                (l_ring == MC_MC01_0_RING_ID) &&
-                ((l_sat_id >= MC_DIR_SAT_ID_SRQ_0) && (l_sat_id <= MC_DIR_SAT_ID_ECC64_3)))
-            {
-                o_chipUnitRelated = true;
-                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
-                                            (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
-                                            (l_sat_id % 4)));
-            }
+                // PU_MCA_CHIPUNIT (mc)
+                // mca: 0..7
+                if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID) &&
+                    (l_ring == MC_MC01_0_RING_ID) &&
+                    ((l_sat_id >= MC_DIR_SAT_ID_SRQ_0) && (l_sat_id <= MC_DIR_SAT_ID_ECC64_3)))
+                {
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
+                                                (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
+                                                (l_sat_id % 4)));
+                }
 
-            // PU_MCA_CHIPUNIT (iomc)
-            // mca: 0..7
-            if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
-                (l_port == UNIT_PORT_ID) &&
-                ((l_ring >= MC_IOM01_0_RING_ID) && (l_ring <= MC_IOM23_1_RING_ID)) &&
-                (l_sat_id == MC_IND_SAT_ID))
+                // PU_MCA_CHIPUNIT (iomc)
+                // mca: 0..7
+                if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID) &&
+                    ((l_ring >= MC_IOM01_0_RING_ID) && (l_ring <= MC_IOM23_1_RING_ID)) &&
+                    (l_sat_id == MC_IND_SAT_ID))
+                {
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
+                                                (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
+                                                (l_ring - MC_IOM01_0_RING_ID)));
+                }
+            }
+            else
             {
-                o_chipUnitRelated = true;
-                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MCA_CHIPUNIT,
-                                            (4 * (l_chiplet_id - MC01_CHIPLET_ID)) +
-                                            (l_ring - MC_IOM01_0_RING_ID)));
+                //==== CUMULUS =====
+                // Figtree references: mc_top_baseaddr.fig, e9_uchip_offset.fig
+                //-------------------------------------------
+                // MC
+                //-------------------------------------------
+                // MC            07     08     0xC(!0xD)
+                // MC            08     08     0xC(!0xD)
+                //Probably any other chipelt 07/08 registers that don't fall into the DMI target range
+                if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                    ( ( (l_port == UNIT_PORT_ID) &&
+                        (
+                            ( (l_ring == P9C_MC_BIST_RING_ID) &&
+                              (l_sat_id != P9C_SAT_ID_CHAN_MCBIST)
+                            ) ||
+                            ( (l_ring == MC_PERV_RING_ID) || //Translate MC perv regs with MC
+                              (l_ring == XB_PSCM_RING_ID) ||
+                              (l_ring == MC_MCTRA_0_RING_ID)
+                            ) ||
+                            ( (l_ring == P9C_MC_IO_RING_ID) &&
+                              (l_sat_id == MC_IND_SAT_ID) &&
+                              (l_sat_offset != P9C_MC_OFFSET_IND)
+                            )
+                        )
+                      ) || //Translate TRA regs with MCBIST
+                      (l_port != UNIT_PORT_ID)
+                    ) )   //Translate MC perv regs with MCBIST
+                {
+
+                    o_chipUnitRelated = true;
+                    o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MC_CHIPUNIT,
+                                                l_chiplet_id - MC01_CHIPLET_ID));
+
+                }
+
+                if (((l_chiplet_id == N3_CHIPLET_ID) || (l_chiplet_id == N1_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID) &&
+                    (l_ring == N3_MC01_0_RING_ID) &&
+                    (l_sat_id == P9C_N3_MCS01_SAT_ID || l_sat_id == P9C_N3_MCS23_SAT_ID))
+                {
+                    //-------------------------------------------
+                    // DMI
+                    //-------------------------------------------
+                    //SCOM3   (See mc_clscom_rlm.fig <= 0xB vs mc_scomfir_rlm.fig > 0xB)
+                    //DMI0           05     02       0   0x2X (X <= 0xB)
+                    //DMI1           05     02       0   0x3X (X <= 0xB)
+                    //DMI2           05     02       2   0x2X (X <= 0xB)
+                    //DMI3           05     02       2   0x3X (X <= 0xB)
+                    //DMI4           03     02       0   0x2X (X <= 0xB)
+                    //DMI5           03     02       0   0x3X (X <= 0xB)
+                    //DMI6           03     02       2   0x2X (X <= 0xB)
+                    //DMI7           03     02       2   0x3X (X <= 0xB)
+                    if ((0x20 <= l_sat_offset && l_sat_offset <= 0x2B) ||
+                        (0x30 <= l_sat_offset && l_sat_offset <= 0x3B))
+                    {
+                        uint8_t l_off_nib0 = (l_sat_offset >> 4);
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_DMI_CHIPUNIT,
+                                                    ((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (4)) +
+                                                    (l_off_nib0 - 2) + l_sat_id));
+
+                    }
+                    //-------------------------------------------
+                    // MI
+                    //-------------------------------------------
+                    //          Chiplet   Ring   Satid   Off
+                    //MCS0           05     02       0   !SCOM3
+                    //MCS1           05     02       2   !SCOM3
+                    //MCS2           03     02       0   !SCOM3
+                    //MCS3           03     02       2   !SCOM3
+                    else
+                    {
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_MI_CHIPUNIT,
+                                                    (l_sat_id / 2) +
+                                                    ((l_chiplet_id == N3_CHIPLET_ID) ? (0) : (2))));
+                    }
+
+                }
+
+                if (((l_chiplet_id == MC01_CHIPLET_ID) || (l_chiplet_id == MC23_CHIPLET_ID)) &&
+                    (l_port == UNIT_PORT_ID))
+                {
+                    //-------------------------------------------
+                    // DMI
+                    //-------------------------------------------
+                    //SCOM1,2
+                    //DMI0           07     02       0
+                    //DMI1           07     02       1
+                    //DMI2           07     02       2
+                    //DMI3           07     02       3
+                    //DMI4           08     02       0
+                    //DMI5           08     02       1
+                    //DMI6           08     02       2
+                    //DMI7           08     02       3
+                    if (l_ring == P9C_MC_CHAN_RING_ID)
+                    {
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_DMI_CHIPUNIT,
+                                                    ((l_chiplet_id == MC01_CHIPLET_ID ? (0) : (4))) +
+                                                    l_sat_id));
+
+                    }
+
+                    //SCOM4
+                    //DMI0           07     08     0xD   0x0X
+                    //DMI1           07     08     0xD   0x1X
+                    //DMI2           07     08     0xD   0x2X
+                    //DMI3           07     08     0xD   0x3X
+                    //DMI4           08     08     0xD   0x0X
+                    //DMI5           08     08     0xD   0x1X
+                    //DMI6           08     08     0xD   0x2X
+                    //DMI7           08     08     0xD   0x3X
+                    if (l_ring == P9C_MC_BIST_RING_ID && l_sat_id == P9C_SAT_ID_CHAN_MCBIST)
+                    {
+                        uint8_t l_off_nib0 = (l_sat_offset >> 4);
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_DMI_CHIPUNIT,
+                                                    ((l_chiplet_id == MC01_CHIPLET_ID ? (0) : (4))) +
+                                                    l_off_nib0));
+
+                    }
+
+                    //-------------------------------------------
+                    // DMI IO
+                    //-------------------------------------------
+                    //          Chiplet   Ring   Satid    Off    RXTXGrp
+                    //DMI0           07     04       0   0x3F       0x00
+                    //DMI1           07     04       0   0x3F       0x01
+                    //DMI2           07     04       0   0x3F       0x02
+                    //DMI3           07     04       0   0x3F       0x03
+                    //DMI4           08     04       0   0x3F       0x00
+                    //DMI5           08     04       0   0x3F       0x01
+                    //DMI6           08     04       0   0x3F       0x02
+                    //DMI7           08     04       0   0x3F       0x03
+
+                    //DMI0           07     04       0   0x3F       0x20
+                    //DMI1           07     04       0   0x3F       0x21
+                    //DMI2           07     04       0   0x3F       0x22
+                    //DMI3           07     04       0   0x3F       0x23
+                    //DMI4           08     04       0   0x3F       0x20
+                    //DMI5           08     04       0   0x3F       0x21
+                    //DMI6           08     04       0   0x3F       0x22
+                    //DMI7           08     04       0   0x3F       0x23
+                    if (l_ring == P9C_MC_IO_RING_ID && l_sat_id == MC_IND_SAT_ID &&
+                        l_sat_offset == P9C_MC_OFFSET_IND )
+                    {
+                        uint32_t l_rxtx_grp = l_scom.get_rxtx_group_id();
+
+                        if (l_rxtx_grp >= 0x20)
+                        {
+                            l_rxtx_grp -= 0x20;
+                        }
+
+                        o_chipUnitRelated = true;
+                        o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_DMI_CHIPUNIT,
+                                                    ((l_chiplet_id == MC01_CHIPLET_ID ? (0) : (4))) +
+                                                    l_rxtx_grp));
+
+                    }
+
+                }
+
             }
 
             // PU_NV_CHIPUNIT