Risk level 3/4/5 support: Step 1 - backward compatibility and v6 image

- Introducing RV_RL3/4/5 ring variant (RV) support for EC/EQ chiplets.
- Dropping RV support for all chiplet's instance rings which saves 456
  Quad bytes and 58 Nest bytes in Seeprom's TOR slots (compared to
  master).
- Each additional risk level adds 144 bytes in Seeprom TOR slots.
- Various changes to data names associated with ring variants to
  clarify that the notion of ring variants is now specific only to
  Common rings while Instance rings only have the BASE variant.
- Also, removed backwards compatibility to TOR v5, i.e. from before
  we introduced RL2 in february. Assumption is that all images/drivers
  used in fips910/920 and OP920 are TOR v6.
- This commit produces a TOR v6 image to ensure EKB FSP CI success.

Key_Cronus_Test=XIP_REGRESS

Change-Id: Icfcb1e68fd74a10ffc48ee7a5da528a8042ef3b1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56973
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56983
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 21 insertions, 16 deletions

diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H
index 7b60d5aed..832608ec1 100644
--- a/src/import/chips/common/utils/imageProcs/common_ringId.H
+++ b/src/import/chips/common/utils/imageProcs/common_ringId.H
@@ -83,7 +83,7 @@ typedef uint8_t   myBoolean_t;      // false:0, true:1, undefined:UNDEFINED_BOOL
 typedef struct
 {
     uint32_t   magic;       // =TOR_MAGIC_xyz
-    uint8_t    version;     // =TOR_VERSION
+    uint8_t    version;     // =TOR version
     ChipType_t chipType;    // Value from ChipType enum
     uint8_t    ddLevel;     // Actual DD level of ringSection
     uint8_t    undefined;
@@ -121,7 +121,8 @@ typedef uint16_t TorRingOffset_t;  // Offset value to actual ring
 //#define TOR_VERSION  3  // Added TOR magic header.
 //#define TOR_VERSION  4  // TOR API code restructuring.
 //#define TOR_VERSION  5  // Removed TOR-level DD handling.
-#define TOR_VERSION  6  // Added additional runtime risk level (RL2)
+//#define TOR_VERSION  6  // Added additional runtime risk level (RL2)
+#define TOR_VERSION  7  // Added three more runtime risk levels (RL3/4/5)
 
 // TOR Magic values for top-level TOR ringSection and sub-ringSections
 enum TorMagicNum
@@ -196,7 +197,7 @@ typedef struct
     uint32_t     scanScomAddress;
 } GenRingIdList;
 
-// P9 PPE types supported.
+// PPE types supported.
 // - This enum also reflects the order with which they appear in the HW image's .rings section.
 // - Do  NOT  make changes to the values or order of this enum.
 enum PpeType
@@ -207,28 +208,32 @@ enum PpeType
     NUM_PPE_TYPES = 0x03
 };
 
-// P9 ring variants supported.
+// Ring variants supported.
 // - This enum also reflects the order with which they appear in various images' .rings section.
 // - Do  NOT  make changes to the values or order of this enum.
 enum RingVariant
 {
     RV_BASE     = 0x00,
     RV_CC       = 0x01,
-    RV_RL       = 0x02,
-    RV_RL2      = 0x03,
-    NUM_RING_VARIANTS = 0x04,
+    RV_RL       = 0x02,  // Kernel and user protection
+    RV_RL2      = 0x03,  // Kernel only protection
+    RV_RL3      = 0x04,  // Rugby v4
+    RV_RL4      = 0x05,  // Java performance
+    RV_RL5      = 0x06,  // Spare
+    NUM_RING_VARIANTS = 0x07,
 };
 
 extern const char* ppeTypeName[];
 extern const char* ringVariantName[];
 
+// Variant order for Common rings
 typedef struct
 {
-    RingVariant_t  variant[4];
+    RingVariant_t  variant[NUM_RING_VARIANTS];
 } RingVariantOrder;
 
 
-// P9 ring types supported.
+// Ring types supported.
 // - This enum also reflects the order with which they appear in various images' .rings section.
 // - Do  NOT  make changes to the values or order of this enum.
 enum RingType
@@ -247,21 +252,21 @@ enum RingBlockType
 
 typedef struct
 {
-    // This is the chiplet-ID of the first instance of the Chiplet
+    // Chiplet ID of the first instance of the Chiplet
     uint8_t iv_base_chiplet_number;
 
-    // The no.of common rings for the Chiplet
+    // Number of common rings for the Chiplet
     uint8_t iv_num_common_rings;
 
-    // The no.of instance rings for the Chiplet (w/different ringId values)
+    // Number of instance rings for the Chiplet (w/different ringId values)
     uint8_t iv_num_instance_rings;
 
-    // The no.of instance rings for the Chiplet (w/different ringId values
+    // Number of instance rings for the Chiplet (w/different ringId values
     // AND different scanAddress values)
     uint8_t iv_num_instance_rings_scan_addrs;
 
-    // The no.of ring variants
-    uint8_t iv_num_ring_variants;
+    // Number of variants for common rings (instance rings only have BASE variant)
+    uint8_t iv_num_common_ring_variants;
 } ChipletData_t;
 
 // This is used to Set (Mark) the left-most bit
@@ -351,7 +356,7 @@ int ringid_get_properties( ChipType_t         i_chipType,
                            GenRingIdList**    o_ringIdListInstance,
                            RingVariantOrder** o_ringVariantOrder,
                            RingProperties_t** o_ringProps,
-                           uint8_t*           o_numVariants );
+                           uint8_t*           o_numVariants);
 
 #endif  // _COMMON_RINGID_H_