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| author | Luke Mulkey <lwmulkey@us.ibm.com> | 2017-07-21 09:45:43 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-19 23:59:09 -0400 |
| commit | aa6a192bd553a6b7faef90874d31da05407cfb56 (patch) | |
| tree | 4ecf21f2a167cc1b0ca73d86ff07b37e010ce799 /src/import/chips/centaur | |
| parent | 11108f43887202522217b92d448880df0fef05e5 (diff) | |
| download | talos-hostboot-aa6a192bd553a6b7faef90874d31da05407cfb56.tar.gz talos-hostboot-aa6a192bd553a6b7faef90874d31da05407cfb56.zip | |
Add ddr3 support back into mss_freq
Change-Id: I39005fb3f4acf38dce9a91571563ba8c4c0e41a2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43430
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44704
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur')
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C index 93c21029b..283a4a456 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_freq.C @@ -164,6 +164,30 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI continue; } } + else + { + // DDR3 ONLY + FAPI_DBG("DDR3 detected"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_MTB_DIVIDEND, l_dimm, l_spd_mtb_dividend), + "Unable to read SPD Medium Timebase Dividend."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_MTB_DIVISOR, l_dimm, l_spd_mtb_divisor), + "Unable to read SPD Medium Timebase Divisor."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_FTB_DIVIDEND, l_dimm, l_spd_ftb_dividend), + "Unable to read the SPD FTB dividend"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_FTB_DIVISOR, l_dimm, l_spd_ftb_divisor), + "Unable to read the SPD FTB divisor"); + FAPI_ASSERT((l_spd_mtb_dividend != 0) && (l_spd_mtb_divisor != 0) && (l_spd_ftb_dividend != 0) + && (l_spd_ftb_divisor != 0), + fapi2::CEN_MSS_UNSUPPORTED_SPD_DATA_DDR3(). + set_MTB_DIVIDEND(l_spd_mtb_dividend). + set_MTB_DIVISOR(l_spd_mtb_divisor). + set_FTB_DIVIDEND(l_spd_ftb_dividend). + set_FTB_DIVISOR(l_spd_ftb_divisor). + set_DIMM_TARGET(l_dimm), + "Invalid data received from SPD within MTB/FTB Dividend, MTB/FTB Divisor"); + + } // common to both DDR3 & DDR4 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_TCKMIN, l_dimm, l_spd_min_tck_MTB)); @@ -192,6 +216,7 @@ fapi2::ReturnCode p9c_mss_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHI set_MIN_TCK(l_spd_min_tck_MTB). set_MIN_TAA(l_spd_min_taa_MTB). set_DIMM_TARGET(l_dimm). + set_TARGET(i_target_memb), "Invalid data received from SPD within TCK Min, or TAA Min"); continue; |
