diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2017-08-21 12:36:55 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-05 23:52:43 -0400 |
| commit | 4fc93481f03389fdb1283d5394649b8d63b57b91 (patch) | |
| tree | df94873dea09d4687d0df256ec1ed0118bf0f791 /src/import/chips/centaur | |
| parent | 5a98fa1055a950625f73ef0501904c9428cb1a2c (diff) | |
| download | talos-hostboot-4fc93481f03389fdb1283d5394649b8d63b57b91.tar.gz talos-hostboot-4fc93481f03389fdb1283d5394649b8d63b57b91.zip | |
permit IPL of Centaur with no attached DIMMs, MBAs
p9c_mss_scominit
p9c_mss_draminit
Relax check to permit zero MBAs
p9_cen_ref_clk_enable
For Cronus, derive set of viable Centaurs from those
connected to present DMI child targets
Change-Id: Icca51d2ea1590ecc75c8daa4a5c5ca35ccc9dfb9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44925
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: LUCAS W. MULKEY <lwmulkey@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44927
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur')
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C | 5 | ||||
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C | 7 |
2 files changed, 0 insertions, 12 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C index d430b2831..5bb6919f2 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C @@ -70,11 +70,6 @@ extern "C" { fapi2::buffer<uint64_t> l_mba01_ref0q_data_buffer_64; // Get associated MBA's on this centaur const auto l_mbaChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MBA>(); - FAPI_ASSERT(l_mbaChiplets.size() == MAX_MBA_PER_CEN, - fapi2::CEN_MSS_SCOMINIT_NUM_MBA_ERROR(). - set_NUM_MBAS(l_mbaChiplets.size()). - set_TARGET(i_target), - "Not two MBAs configured on %s", mss::c_str(i_target)); // Step One: Set IML COMPLETE FAPI_INF( "+++ Setting IML Complete +++"); diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C index fe8100c1b..d43823c77 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_scominit.C @@ -59,13 +59,6 @@ extern "C" { const auto l_mba_targets = i_target.getChildren<fapi2::TARGET_TYPE_MBA>(); const auto l_l4_targets = i_target.getChildren<fapi2::TARGET_TYPE_L4>(fapi2::TARGET_STATE_PRESENT); - FAPI_ASSERT_NOEXIT(l_mba_targets.size() == MAX_MBA_PER_CEN, - fapi2::CEN_MSS_SCOMINIT_NUM_MBA_ERROR(). - set_MEMBUF(i_target). - set_NUM_MBAS(l_mba_targets.size()), - "getChildren returned %d functional MBAs, expected 2.", - l_mba_targets.size()); - FAPI_ASSERT(l_l4_targets.size() > 0, fapi2::CEN_MSS_SCOMINIT_NUM_L4_ERROR(). set_MEMBUF(i_target). |
