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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-04-26 15:24:59 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-29 12:31:18 -0400 |
| commit | 3363a36c1d272ab0035be5d9652bf9339c4e7e5e (patch) | |
| tree | 3505c3fbb7875e3f1dbaeb9ae05fb3832f60c6a3 /src/import/chips/centaur/procedures/hwp | |
| parent | d070d9a251bd242eb2a257857398b08ea58f5bf6 (diff) | |
| download | talos-hostboot-3363a36c1d272ab0035be5d9652bf9339c4e7e5e.tar.gz talos-hostboot-3363a36c1d272ab0035be5d9652bf9339c4e7e5e.zip | |
PLL updates for Cumulus simulation testing
assuming 32u32d refclock inputs, program Centaur mesh clocks for:
nest_nclk - 8u8d
mbc_nclk - 16u16d
mem_nclk - 12u12d
phyn_nclk - 24u24d
phys_nclk - 24u24d
slow down Cumulus nest/quad clocks based on nest frequency:
nest_gckn - 8u8d
core_gckn - 4u4d
cache_gckn - 8u8d
Change-Id: I44ad246bb565b505f8388f40861171610b610986
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39731
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45030
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/centaur/procedures/hwp')
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/initfiles/centaur_mem_pll_scan.C | 8 | ||||
| -rw-r--r-- | src/import/chips/centaur/procedures/hwp/initfiles/centaur_nest_pll_scan.C | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mem_pll_scan.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mem_pll_scan.C index f2d43fd3c..93104de29 100644 --- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mem_pll_scan.C +++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_mem_pll_scan.C @@ -30,7 +30,7 @@ using namespace fapi2; constexpr uint64_t literal_1 = 1; -constexpr uint64_t literal_0x128000000A0060D3 = 0x128000000A0060D3; +constexpr uint64_t literal_0x128000000A0040D5 = 0x128000000A0040D5; constexpr uint64_t literal_1066 = 1066; constexpr uint64_t literal_0 = 0; constexpr uint64_t literal_0x128000000A0030D2 = 0x128000000A0030D2; @@ -40,7 +40,7 @@ constexpr uint64_t literal_1600 = 1600; constexpr uint64_t literal_0x128000000A0030D1 = 0x128000000A0030D1; constexpr uint64_t literal_1866 = 1866; constexpr uint64_t literal_0x128000000A0150D5 = 0x128000000A0150D5; -constexpr uint64_t literal_0x7000000200040000 = 0x7000000200040000; +constexpr uint64_t literal_0xB000000200040000 = 0xB000000200040000; constexpr uint64_t literal_0x5000000200040002 = 0x5000000200040002; constexpr uint64_t literal_0x3000000200040002 = 0x3000000200040002; constexpr uint64_t literal_0xB000000200040002 = 0xB000000200040002; @@ -66,7 +66,7 @@ fapi2::ReturnCode centaur_mem_pll_scan(const fapi2::Target<fapi2::TARGET_TYPE_ME if (l_def_IS_SIM) { - l_PLLMEM_PLL_CNTRL0.insertFromRight<uint64_t>(literal_0x128000000A0060D3, 0, 64); + l_PLLMEM_PLL_CNTRL0.insertFromRight<uint64_t>(literal_0x128000000A0040D5, 0, 64); l_PLLMEM_PLL_CNTRL0_update = true; } else if ((l_def_IS_HW && (l_def_MEMB_MEM_FREQ == literal_1066))) @@ -100,7 +100,7 @@ fapi2::ReturnCode centaur_mem_pll_scan(const fapi2::Target<fapi2::TARGET_TYPE_ME if (l_def_IS_SIM) { - l_PLLMEM_PLL_CNTRL1.insertFromRight<uint64_t>(literal_0x7000000200040000, 0, 64); + l_PLLMEM_PLL_CNTRL1.insertFromRight<uint64_t>(literal_0xB000000200040000, 0, 64); l_PLLMEM_PLL_CNTRL1_update = true; } else if ((l_def_IS_HW && (l_def_MEMB_MEM_FREQ == literal_1066))) diff --git a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_nest_pll_scan.C b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_nest_pll_scan.C index b31077aea..d364ac658 100644 --- a/src/import/chips/centaur/procedures/hwp/initfiles/centaur_nest_pll_scan.C +++ b/src/import/chips/centaur/procedures/hwp/initfiles/centaur_nest_pll_scan.C @@ -30,7 +30,7 @@ using namespace fapi2; constexpr uint64_t literal_1 = 1; -constexpr uint64_t literal_0x13CB1402001C0009 = 0x13CB1402001C0009; +constexpr uint64_t literal_0x13CAB402001C0009 = 0x13CAB402001C0009; constexpr uint64_t literal_2000 = 2000; constexpr uint64_t literal_0 = 0; constexpr uint64_t literal_0x18469406001C0048 = 0x18469406001C0048; @@ -60,7 +60,7 @@ fapi2::ReturnCode centaur_nest_pll_scan(const fapi2::Target<fapi2::TARGET_TYPE_M if (l_def_IS_SIM) { - l_DMI_DMIPLL_CWRAP_PLL_CNTRL0.insertFromRight<uint64_t>(literal_0x13CB1402001C0009, 0, 64); + l_DMI_DMIPLL_CWRAP_PLL_CNTRL0.insertFromRight<uint64_t>(literal_0x13CAB402001C0009, 0, 64); l_DMI_DMIPLL_CWRAP_PLL_CNTRL0_update = true; } else if ((l_def_IS_HW && (l_def_NEST_FREQ == literal_2000))) |
