Use SBE Setting of Thread Count or Fail

This commit takes out the workaround of using a default setting
of a thread count if the SBE didn't set the right value in a
scratch register.  The current SBE code now does this, and we
will now fail if for some reason the value isn't set.  This commit
also includes sim action file updates to model this behavior.

Change-Id: I83608c402fac675c0287fa3ce38cf75237bcff26
RTC: 63991
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5255
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 62 insertions, 1 deletions

diff --git a/src/build/citest/etc/patches/p8.act_sbe_thread_count_patch b/src/build/citest/etc/patches/p8.act_sbe_thread_count_patch
new file mode 100644
index 000000000..0a229eb19
--- /dev/null
+++ b/src/build/citest/etc/patches/p8.act_sbe_thread_count_patch
@@ -0,0 +1,30 @@
+*** ORIG/p8.act	2013-06-28 15:09:38.397876370 -0500
+--- NEW/p8.act	2013-06-28 16:36:03.653781869 -0500
+***************
+*** 157,168 ****
+    EFFECT: TARGET=[PROCREG(msr, 4, 6)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
+    EFFECT: TARGET=[PROCREG(nia, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]# NIA to default
+    EFFECT: TARGET=[PROCREG(msr, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
+  
+    #ds01 Discover the secure state and save it away
+    EFFECT: TARGET=[LOGIC(0xFF0CC004)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00010005)] MASK=[LITERAL(64,80000000 00000000)] SHIFT=[63]
+    # ds01 ch128 Load Hostboot base image from offset in MBOX SCRATCH3 reg (0x3A)
+    EFFECT: TARGET=[MODULE(sbeStart, FSIMBOX(0x3A), LOGIC(0xFF0CC004), 4)] OP=[MODULECALL] #dds129 
+!   
+    ##############################################################################
+    # Phase 2: Start SBE
+    ##############################################################################
+--- 157,169 ----
+    EFFECT: TARGET=[PROCREG(msr, 4, 6)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
+    EFFECT: TARGET=[PROCREG(nia, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]# NIA to default
+    EFFECT: TARGET=[PROCREG(msr, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
++   EFFECT: TARGET=[PROCREG(scratch, 4,7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0000FF00 00000000)]# Thread Count
+  
+    #ds01 Discover the secure state and save it away
+    EFFECT: TARGET=[LOGIC(0xFF0CC004)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00010005)] MASK=[LITERAL(64,80000000 00000000)] SHIFT=[63]
+    # ds01 ch128 Load Hostboot base image from offset in MBOX SCRATCH3 reg (0x3A)
+    EFFECT: TARGET=[MODULE(sbeStart, FSIMBOX(0x3A), LOGIC(0xFF0CC004), 4)] OP=[MODULECALL] #dds129 
+! 
+    ##############################################################################
+    # Phase 2: Start SBE
+    ##############################################################################
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index 538335cb5..456724f60 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -30,3 +30,13 @@ Add POR setting for TBROM scom register
   Indirectly: p8_slave.por, s1_master.por, s1_slave.por
 -Coreq: None
 
+Add action for SBE to set Thread Count
+-RTC: 76712
+-CMVC: 889344
+- Files
+  src/build/citest/etc/workarounds.postsimsetup
+  src/build/citest/etc/patches/patchlist.txt
+  src/build/citest/etc/patches/p8.act_sbe_thread_count_patch
+  src/build/citest/etc/patches/s1.act_sbe_thread_count_patch
+-Coreq: None
+
diff --git a/src/build/citest/etc/patches/s1.act_sbe_thread_count_patch b/src/build/citest/etc/patches/s1.act_sbe_thread_count_patch
new file mode 100644
index 000000000..2d21f27ac
--- /dev/null
+++ b/src/build/citest/etc/patches/s1.act_sbe_thread_count_patch
@@ -0,0 +1,12 @@
+*** ORIG/s1.act	2013-06-28 14:54:22.409519345 -0500
+--- NEW/s1.act	2013-06-28 16:36:15.777409068 -0500
+***************
+*** 118,123 ****
+--- 118,124 ----
+    EFFECT: TARGET=[PROCREG(msr, 4, 6)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
+    EFFECT: TARGET=[PROCREG(nia, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000100)]# NIA to default
+    EFFECT: TARGET=[PROCREG(msr, 4, 7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,D0000000 00000000)]# MSR to default
++   EFFECT: TARGET=[PROCREG(scratch, 4,7)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0000FF00 00000000)]# Thread Count
+  
+    #ds01 Discover the secure state and save it away
+    EFFECT: TARGET=[LOGIC(0xFF0CC004)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00010005)] MASK=[LITERAL(64,80000000 00000000)] SHIFT=[63]
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 191f06aed..ee25aa5ae 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -41,7 +41,6 @@ cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_ex_l3purge.act >> \
 cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_ex_l3purge.act >> \
     $sb/simu/data/cec-chip/s1_ex.act
 
-
 echo "+++ Updating POR files for Secure ROM Support (removed with RTC 72729)"
 mkdir -p $sb/simu/data/cec-chip/
 grep -v 0x02020017 $BACKING_BUILD/src/simu/data/cec-chip/p8_master.por > \
@@ -60,3 +59,13 @@ cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_master.por >> \
     $sb/simu/data/cec-chip/s1_master.por
 cat $HOSTBOOTROOT/src/build/citest/etc/patches/p8_master.por >> \
     $sb/simu/data/cec-chip/s1_slave.por
+
+echo "+++ Updating actions for Thread Count(CMVC 889344)"
+mkdir -p $sb/simu/data/cec-chip
+cp $BACKING_BUILD/src/simu/data/cec-chip/p8.act $sb/simu/data/cec-chip
+cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip
+patch $sb/simu/data/cec-chip/p8.act \
+      $HOSTBOOTROOT/src/build/citest/etc/patches/p8.act_sbe_thread_count_patch
+patch $sb/simu/data/cec-chip/s1.act \
+      $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act_sbe_thread_count_patch
+