Applied final PNOR layout

Change-Id: Iec0bc0506c1f676ec8ebec821a19c3246c46838f
RTC:65006
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7830
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 156 insertions, 103 deletions

diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml
index f63d214bd..4fcc42a51 100644
--- a/src/build/buildpnor/defaultPnorLayout.xml
+++ b/src/build/buildpnor/defaultPnorLayout.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2014              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -60,115 +60,117 @@ Layout Description
         <sideBOffset>0x8000</sideBOffset>
     </metadata>
     <section>
-        <description>Hostboot Extended image (5MB)</description>
-        <eyeCatch>HBI</eyeCatch>
+        <description>Hostboot Error Logs (144K)</description>
+        <eyeCatch>HBEL</eyeCatch>
         <physicalOffset>0x10000</physicalOffset>
-        <physicalRegionSize>0x500000</physicalRegionSize>
-        <sha512Version/>
-        <side>A</side>  <!-- Choices: A, B -->
+        <physicalRegionSize>0x24000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Centaur SBE (512K)</description>
-        <eyeCatch>SBEC</eyeCatch>
-        <physicalOffset>0xA10000</physicalOffset>
-        <physicalRegionSize>0x80000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Guard Data (20K)</description>
+        <eyeCatch>GUARD</eyeCatch>
+        <physicalOffset>0x58000</physicalOffset>
+        <physicalRegionSize>0x5000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>SBE-IPL (Staging Area) (256K)</description>
-        <eyeCatch>SBE</eyeCatch>
-        <physicalOffset>0xB10000</physicalOffset>
-        <physicalRegionSize>0x40000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Hostboot Data (1.125M)</description>
+        <eyeCatch>HBD</eyeCatch>
+        <physicalOffset>0x5D000</physicalOffset>
+        <physicalRegionSize>0x120000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Sleep Winkle Ref Image (1MB)</description>
-        <eyeCatch>WINK</eyeCatch>
-        <physicalOffset>0xB90000</physicalOffset>
-        <physicalRegionSize>0x100000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>DIMM JEDEC (288K)</description>
+        <eyeCatch>DJVPD</eyeCatch>
+        <!--NOTE: MUST update standalone.simics if offset changes -->
+         <physicalOffset>0x17D000</physicalOffset>
+        <physicalRegionSize>0x48000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Payload (20MB)</description>
-        <eyeCatch>PAYLOAD</eyeCatch>
-        <physicalOffset>0xD90000</physicalOffset>
-        <physicalRegionSize>0x1400000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Module VPD (576K)</description>
+        <eyeCatch>MVPD</eyeCatch>
+        <!--NOTE: MUST update standalone.simics if offset changes -->
+        <physicalOffset>0x1C5000</physicalOffset>
+        <physicalRegionSize>0x90000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Hostboot Runtime Services for Sapphire (2MB)</description>
-        <eyeCatch>HBRT</eyeCatch>
-        <physicalOffset>0x2190000</physicalOffset>
-        <physicalRegionSize>0x200000</physicalRegionSize>
-        <side>A</side>
+        <description>Centaur VPD (288K)</description>
+        <eyeCatch>CVPD</eyeCatch>
+        <!--NOTE: MUST update standalone.simics if offset changes -->
+        <physicalOffset>0x255000</physicalOffset>
+        <physicalRegionSize>0x48000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Special PNOR Test Space (32K)</description>
-        <eyeCatch>TEST</eyeCatch>
-        <physicalOffset>0x3590000</physicalOffset>
-        <physicalRegionSize>0x8000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
-        <testonly/>
+        <description>Hostboot Extended image (5.625MB)</description>
+        <eyeCatch>HBI</eyeCatch>
+        <physicalOffset>0x29D000</physicalOffset>
+        <physicalRegionSize>0x5A0000</physicalRegionSize>
+        <sha512Version/>
         <ecc/>
     </section>
     <section>
-        <description>Hostboot Data (1M)</description>
-        <eyeCatch>HBD</eyeCatch>
-        <physicalOffset>0x3B82000</physicalOffset>
-        <physicalRegionSize>0x100000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Centaur SBE (576K)</description>
+        <eyeCatch>SBEC</eyeCatch>
+        <physicalOffset>0x83D000</physicalOffset>
+        <physicalRegionSize>0x90000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Guard Data (16K)</description>
-        <eyeCatch>GUARD</eyeCatch>
-        <physicalOffset>0x3D82000</physicalOffset>
-        <physicalRegionSize>0x4000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>SBE-IPL (Staging Area) (288K)</description>
+        <eyeCatch>SBE</eyeCatch>
+        <physicalOffset>0x8CD000</physicalOffset>
+        <physicalRegionSize>0x48000</physicalRegionSize>
+        <sha512perEC/>
+        <ecc/>
     </section>
     <section>
-        <description>Hostboot Error Logs (128K)</description>
-        <eyeCatch>HBEL</eyeCatch>
-        <physicalOffset>0x3D8A000</physicalOffset>
-        <physicalRegionSize>0x20000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Sleep Winkle Ref Image (1.125MB)</description>
+        <eyeCatch>WINK</eyeCatch>
+        <physicalOffset>0x915000</physicalOffset>
+        <physicalRegionSize>0x120000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>DIMM JEDEC (256K)</description>
-        <eyeCatch>DJVPD</eyeCatch>
-      	<!--NOTE: MUST update standalone.simics if offset changes -->
-         <physicalOffset>0x3DCA000</physicalOffset>
-        <physicalRegionSize>0x40000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Hostboot Runtime Services for Sapphire (2.25MB)</description>
+        <eyeCatch>HBRT</eyeCatch>
+        <physicalOffset>0xA35000</physicalOffset>
+        <physicalRegionSize>0x240000</physicalRegionSize>
+        <sha512Version/>
+        <ecc/>
     </section>
     <section>
-        <description>Module VPD (512K)</description>
-        <eyeCatch>MVPD</eyeCatch>
-       	<!--NOTE: MUST update standalone.simics if offset changes -->
-        <physicalOffset>0x3E0A000</physicalOffset>
-        <physicalRegionSize>0x80000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Payload (22.5MB)</description>
+        <eyeCatch>PAYLOAD</eyeCatch>
+        <physicalOffset>0xC75000</physicalOffset>
+        <physicalRegionSize>0x1680000</physicalRegionSize>
+        <ecc/>
     </section>
     <section>
-        <description>Centaur VPD (256K)</description>
-        <eyeCatch>CVPD</eyeCatch>
-    	<!--NOTE: MUST update standalone.simics if offset changes -->
-        <physicalOffset>0x3E8A000</physicalOffset>
-        <physicalRegionSize>0x40000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <description>Special PNOR Test Space (36K)</description>
+        <eyeCatch>TEST</eyeCatch>
+        <physicalOffset>0x3590000</physicalOffset>
+        <physicalRegionSize>0x9000</physicalRegionSize>
+        <testonly/>
+        <ecc/>
     </section>
     <section>
         <description>Hostboot Base (576K)</description>
+        <!--NOTE: MUST update standalone.simics if offset changes -->
         <eyeCatch>HBB</eyeCatch>
-        <physicalOffset>0x3ECE000</physicalOffset>
+        <physicalOffset>0x3F67000</physicalOffset>
         <physicalRegionSize>0x90000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <sha512Version/>
         <ecc/>
     </section>
     <section>
         <description>Global Data (36K)</description>
         <eyeCatch>GLOBAL</eyeCatch>
-        <physicalOffset>0x3FEE000</physicalOffset>
+        <physicalOffset>0x3FF7000</physicalOffset>
         <physicalRegionSize>0x9000</physicalRegionSize>
-        <side>A</side>  <!-- Choices: A, B -->
+        <ecc/>
     </section>
 </pnor>
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 26f3f2e8d..c5cf334df 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -5,7 +5,7 @@
 #
 # IBM CONFIDENTIAL
 #
-# COPYRIGHT International Business Machines Corp. 2012,2013
+# COPYRIGHT International Business Machines Corp. 2012,2014
 #
 # p1
 #
@@ -37,7 +37,7 @@ DEFAULT_PATH = ${.PATH}
 SRCPATH = ${DEFAULT_PATH:M*src*}
 
 build_all: cp_hbfiles
-install_all: build_sbe_partitions build_pnor_images
+install_all: inject_ecc build_sbe_partitions build_pnor_images
 
 #Some useful search paths
 HBFW_OBJPATH = ${.PATH:M*obj*}
@@ -53,6 +53,9 @@ ENGD_OBJPATH = ${HBFW_OBJPATH:S/hbfw\/img/engd\/href/g}
 BASE_IMAGE = hostboot.bin
 EXT_IMAGE =  hostboot_extended.bin
 HBRT_IMAGE = hostboot_runtime.bin
+HBRT_SHA_IMAGE = hostboot_runtime.sha.bin
+HBRT_HEADER_IMAGE = hostboot_runtime.header.bin
+HBRT_ECC_HEADER_IMAGE = hostboot_runtime.header.bin.ecc
 BASE_IMAGES = ${BASE_IMAGE} ${EXT_IMAGE} ${HBRT_IMAGE}
 BASE_W_HEADER_IMAGE = hostboot.header.bin
 BASE_W_HEADER_ECC_IMAGE = hostboot.header.bin.ecc
@@ -60,15 +63,22 @@ BASE_ECC_IMAGE = hostboot.bin.ecc
 BASE_SHA_IMAGE = hostboot.sha.bin
 EXT_PAD_IMAGE = hostboot_extended.bin.pad
 EXT_ECC_IMAGE = hostboot_extended.bin.ecc
-EXT_ECC_HEADER_IMAGE = hostboot_extended.header.ecc.bin
+EXT_ECC_HEADER_IMAGE = hostboot_extended.header.bin.ecc
 EXT_SHA_IMAGE = hostboot_extended.sha.bin
 EXT_HEADER_IMAGE = hostboot_extended.header.bin
+TEMP_IMAGE = hostboot.temp.bin
 TESTDATA = hbtestdata.bin
 TESTDATA_ECC = hbtestdata.bin.ecc
+HBEL_ECC_IMAGE = hbel.bin.ecc
+GUARD_ECC_IMAGE = guard.bin.ecc
+GOLBAL_ECC_IMAGE = global.bin.ecc
+
 ALL_HB_IMAGES = ${BASE_IMAGES} \
                 ${BASE_W_HEADER_IMAGE} \
                 ${BASE_ECC_IMAGE} ${EXT_ECC_IMAGE} \
                 ${BASE_W_HEADER_ECC_IMAGE} ${BASE_SHA_IMAGE}\
+                ${HBRT_SHA_IMAGE} \
+                ${HBRT_HEADER_IMAGE} ${HBRT_ECC_HEADER_IMAGE} \
                 ${EXT_PAD_IMAGE} \
                 ${EXT_SHA_IMAGE} ${EXT_HEADER_IMAGE} \
                 ${EXT_ECC_HEADER_IMAGE} \
@@ -90,16 +100,31 @@ cp_hbfiles: .SPECTARG
 	# dd command will pad image up to the next 4K page
 	dd if=${EXT_IMAGE} of=${EXT_PAD_IMAGE} ibs=4k count=1280 conv=sync
 	ecc --inject ${EXT_PAD_IMAGE} --output ${EXT_ECC_IMAGE} --p8
-	# add version header w/ sha hash
+	# add version header w/ HBRT sha hash
+	echo -en VERSION\\0 > ${HBRT_SHA_IMAGE}
+	sha512sum ${HBRT_IMAGE} | awk '{print $$1}' | xxd -pr -r >> ${HBRT_SHA_IMAGE}
+	dd if=${HBRT_SHA_IMAGE} of=${TEMP_IMAGE} ibs=4k conv=sync
+	cat ${HBRT_IMAGE} >> ${TEMP_IMAGE}
+	dd if=${TEMP_IMAGE} of=${HBRT_HEADER_IMAGE} ibs=4k conv=sync
+	ecc --inject ${HBRT_HEADER_IMAGE} --output ${HBRT_ECC_HEADER_IMAGE} --p8
+	# add version header w/ HBI sha hash
 	echo -en VERSION\\0 > ${EXT_SHA_IMAGE}
 	sha512sum ${EXT_IMAGE} | awk '{print $$1}' | xxd -pr -r >> ${EXT_SHA_IMAGE}
-	dd if=${EXT_SHA_IMAGE} of=${EXT_HEADER_IMAGE} ibs=4k conv=sync
-	dd if=${EXT_SHA_IMAGE} of=${EXT_ECC_HEADER_IMAGE} ibs=4k conv=sync
-	cat ${EXT_IMAGE} >> ${EXT_HEADER_IMAGE}
-	cat ${EXT_ECC_IMAGE} >> ${EXT_ECC_HEADER_IMAGE}
+	dd if=${EXT_SHA_IMAGE} of=${TEMP_IMAGE} ibs=4k conv=sync
+	cat ${EXT_IMAGE} >> ${TEMP_IMAGE}
+	dd if=${TEMP_IMAGE} of=${EXT_HEADER_IMAGE} ibs=4k conv=sync
+	ecc --inject ${EXT_HEADER_IMAGE} --output ${EXT_ECC_HEADER_IMAGE} --p8
 	# create data for a test partition in pnor
 	dd if=/dev/urandom of=${TESTDATA} bs=1 count=28K
 	ecc --inject ${TESTDATA} --output ${TESTDATA_ECC} --p8
+	# HBEL, GUARD, and GLOBAL ECC
+	dd if=/dev/zero count=128K bs=1 | tr "\000" "\377" > ${TEMP_IMAGE}
+	ecc --inject ${TEMP_IMAGE} --output ${HBEL_ECC_IMAGE} --p8
+	dd if=/dev/zero count=16K bs=1 | tr "\000" "\377" > ${TEMP_IMAGE}
+	ecc --inject ${TEMP_IMAGE} --output ${GUARD_ECC_IMAGE} --p8
+	dd if=/dev/zero count=32K bs=1 | tr "\000" "\377" > ${TEMP_IMAGE}
+	ecc --inject ${TEMP_IMAGE} --output ${GOLBAL_ECC_IMAGE} --p8
+	rm ${TEMP_IMAGE}
 
 clobber_cp_hbfiles:
 	rm -f ${ALL_HB_IMAGES} \
@@ -176,23 +201,39 @@ PNOR_BUILD_SCRIPT = ${buildpnor.pl:P}
 #so need to use tryinclude for now.
 .tryinclude <${.PATH:Ffips_pnor.mk}>
 
-#uncomment the below line to enable ECC in the extended image
-#HOSTBOOT_DEFAULT_SECTIONS = HBB=${BASE_W_HEADER_ECC_IMAGE},HBI=${EXT_ECC_HEADER_IMAGE},HBRT=${HBRT_IMAGE},TEST=${TESTDATA_ECC}
-HOSTBOOT_DEFAULT_SECTIONS = HBB=${BASE_W_HEADER_ECC_IMAGE},HBI=${EXT_HEADER_IMAGE},HBRT=${HBRT_IMAGE},TEST=${TESTDATA_ECC}
+HOSTBOOT_DEFAULT_SECTIONS = HBB=${BASE_W_HEADER_ECC_IMAGE},HBI=${EXT_ECC_HEADER_IMAGE},HBRT=${HBRT_ECC_HEADER_IMAGE},TEST=${TESTDATA_ECC},HBEL=${HBEL_ECC_IMAGE},GUARD=${GUARD_ECC_IMAGE},GLOBAL=${GOLBAL_ECC_IMAGE}
 
 
 HBFW_OBJPATH = ${.PATH:M*obj*}
 ENGD_OBJPATH = ${HBFW_OBJPATH:S/hbfw\/img/engd\/href/g}
 MURANO_TARG_IMG = simics_MURANO_targeting.bin
 VENICE_TARG_IMG = simics_VENICE_targeting.bin
-MURANO_SLW_IMG = ${ENGD_OBJPATH:Fs1.ref_image.bin}
-VENICE_SLW_IMG = ${ENGD_OBJPATH:Fp8.ref_image.bin}
+MURANO_SLW_IMG = ${ENGD_OBJPATH:Fs1.ref_image.hdr.bin}
+VENICE_SLW_IMG = ${ENGD_OBJPATH:Fp8.ref_image.hdr.bin}
+MURANO_LOCAL_SLW_IMG = s1.ref_image.hdr.bin
+VENICE_LOCAL_SLW_IMG = p8.ref_image.hdr.bin
 MURANO_SBE_IMG = s1SbePartition.bin
 VENICE_SBE_IMG = p8SbePartition.bin
 SBEC_IMG = centSbePartition.bin
-MURANO_SECT = HBD=${MURANO_TARG_IMG},SBE=${MURANO_SBE_IMG},SBEC=${SBEC_IMG},WINK=${MURANO_SLW_IMG}
-VENICE_SECT = HBD=${VENICE_TARG_IMG},SBE=${VENICE_SBE_IMG},SBEC=${SBEC_IMG},WINK=${VENICE_SLW_IMG}
-
+TEMP_IMG = temp.bin
+
+INPUT_ECC = ${${MURANO_TARG_IMG}:P} ${${VENICE_TARG_IMG}:P} \
+		${MURANO_LOCAL_SLW_IMG} ${VENICE_LOCAL_SLW_IMG} \
+		${MURANO_SBE_IMG} ${VENICE_SBE_IMG} \
+		${SBEC_IMG}
+
+inject_ecc: build_sbe_partitions
+	# cp file with full path to one with local path
+	cp ${MURANO_SLW_IMG} ${MURANO_LOCAL_SLW_IMG}
+	cp ${VENICE_SLW_IMG} ${VENICE_LOCAL_SLW_IMG}
+	for file in ${INPUT_ECC}; do\
+		dd if=$$file of=${TEMP_IMG} ibs=4k conv=sync; \
+		ecc --inject ${TEMP_IMG} --output $$file.ecc --p8; \
+	done
+	rm ${TEMP_IMG}
+
+MURANO_SECT = HBD=${MURANO_TARG_IMG}.ecc,SBE=${MURANO_SBE_IMG}.ecc,SBEC=${SBEC_IMG}.ecc,WINK=${MURANO_LOCAL_SLW_IMG}.ecc
+VENICE_SECT = HBD=${VENICE_TARG_IMG}.ecc,SBE=${VENICE_SBE_IMG}.ecc,SBEC=${SBEC_IMG}.ecc,WINK=${VENICE_LOCAL_SLW_IMG}.ecc
 
 PNOR_IMG_INFO = \
    murano.pnor:defaultPnorLayout.xml:${MURANO_SECT},${HOSTBOOT_DEFAULT_SECTIONS} \
@@ -246,7 +287,7 @@ clobber_build_pnor_images:
 FLASH_DEST = $(MAKETOP)$(OBJECTDIRTOP)../images/$(CONTEXT)/lab/flash
 FLASH_IMG = ${BASE_IMAGE} ${BASE_ECC_IMAGE}
 
-update_images_for_sandbox: build_sbe_partitions build_pnor_images
+update_images_for_sandbox: inject_ecc build_sbe_partitions build_pnor_images
 	mkdir -p ${FLASH_DEST}
 	#Copy hostboot base image to flash dir
 	${FLASH_IMG:@image@${baseimg:!cd ${FLASH_DEST}; cp -f ${.PATH:F${image}} ${image};!e}@}
diff --git a/src/build/simics/hb-pnor-vpd-preload.pl b/src/build/simics/hb-pnor-vpd-preload.pl
index e951492ef..77fca1868 100755
--- a/src/build/simics/hb-pnor-vpd-preload.pl
+++ b/src/build/simics/hb-pnor-vpd-preload.pl
@@ -6,7 +6,7 @@
 #
 # IBM CONFIDENTIAL
 #
-# COPYRIGHT International Business Machines Corp. 2012,2013
+# COPYRIGHT International Business Machines Corp. 2012,2014
 #
 # p1
 #
@@ -57,6 +57,7 @@ my $sysMVPD = "sysmvpd.dat";
 my $sysCVPD = "syscvpd.dat";
 my $sysSPD = "sysspd.dat";
 
+
 my $MAX_CENT_PER_PROC = 8;
 my $MAX_DIMMS_PER_CENT = 8;
 my $MAX_MCS = 8;
@@ -247,6 +248,7 @@ sub createMVPDData
     my $result;
     my $sourceFile;
     my $sysMVPDFile = "$outputPath/$sysMVPD";
+    my $sysMVPDFileECC = $sysMVPDFile . ".ecc";
 
     if( -e $sysMVPDFile )
     {
@@ -259,7 +261,7 @@ sub createMVPDData
     # If this ever changes, building the MVPD data and SPD data will need to
     # be combined to not duplicate the logic for determining which processors
     # have which DIMMs.
-    
+
     # Create empty processor MVPD chunk.
     $cmd = "echo \"00FFFF: 00\" \| xxd -r \> $emptyMVPD";
     system( $cmd ) == 0 or die "Creating $emptyMVPD failed!";
@@ -288,6 +290,8 @@ sub createMVPDData
     if( -e $sysMVPDFile )
     {
         system( "chmod 775 $sysMVPDFile" );
+        system( "ecc --inject $sysMVPDFile --output $sysMVPDFileECC --p8" );
+        system( "chmod 775 $sysMVPDFileECC" );
     }
     debugMsg( "MVPD Done." );
 }
@@ -303,6 +307,7 @@ sub createCVPDData
     my $result;
     my $sourceFile;
     my $sysCVPDFile = "$outputPath/$sysCVPD";
+    my $sysCVPDFileECC = $sysCVPDFile . ".ecc";
 
     if( -e $sysCVPDFile )
     {
@@ -349,6 +354,8 @@ sub createCVPDData
     if( -e $sysCVPDFile )
     {
         system( "chmod 775 $sysCVPDFile" );
+        system( "ecc --inject $sysCVPDFile --output $sysCVPDFileECC --p8" );
+        system( "chmod 775 $sysCVPDFileECC" );
     }
     debugMsg( "CVPD Done." );
 }
@@ -365,6 +372,7 @@ sub createSPDData
     my $result;
     my $sourceFile;
     my $sysSPDFile = "$outputPath/$sysSPD";
+    my $sysSPDFileECC = $sysSPDFile . ".ecc";
 
     if( -e $sysSPDFile )
     {
@@ -409,6 +417,8 @@ sub createSPDData
     if( -e $sysSPDFile )
     {
         system( "chmod 775 $sysSPDFile" );
+        system( "ecc --inject $sysSPDFile --output $sysSPDFileECC --p8" );
+        system( "chmod 775 $sysSPDFileECC" );
     }
     debugMsg( "SPD Done." );
 }
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index cad7eb796..6831c5bc1 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -8,16 +8,16 @@
 foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) {
     try {
         run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
-            ($pnor).sfc_master_mem.load-file ./sysmvpd.dat 0x3E0A000
-            ($pnor).sfc_master_mem.load-file ./sysspd.dat 0x3DCA000
-            ($pnor).sfc_master_mem.load-file ./syscvpd.dat 0x3E8A000
+            ($pnor).sfc_master_mem.load-file ./sysmvpd.dat.ecc 0x1C5000
+            ($pnor).sfc_master_mem.load-file ./sysspd.dat.ecc 0x17D000
+            ($pnor).sfc_master_mem.load-file ./syscvpd.dat.ecc 0x255000
     } except { echo "ERROR: Failed to preload VPD into PNOR." }
 }
 
-#Write the PNOR MMIO addr into Scratch 2, 0x283A 
-#($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFEF0000  #HB PNOR addr
+#Write the PNOR MMIO addr into Scratch 2, 0x283A
+#($hb_masterproc).proc_lbus_map.write 0x28e8 0xFFF78000  #HB PNOR addr
 foreach $cc in (get-object-list p8_proc) {
-    ($cc).proc_lbus_map.write 0x28e8 0xFFEF0000
+    ($cc).proc_lbus_map.write 0x28e8 0xFFF78000
 }
 
 # Loop through every processor chip
@@ -29,10 +29,10 @@ foreach $cc in (get-object-list p8_proc) {
     @mp="%s.proc_chip"%simenv.cc
     @SIM_get_interface(SIM_get_object(mp),"signal").signal_raise(SIM_get_object(mp))
 
-    #Trigger the flush, load, and SBE start 
+    #Trigger the flush, load, and SBE start
     echo "-Trigger SBE"
     ($cc).proc_lbus_map.write 0x28E0 0x0000F3FF  #NonFunc EX (only 4,5 is good)
-    ($cc).proc_lbus_map.write 0x2848 0x00000FFF  #GP3 0x2812 (flush) 
+    ($cc).proc_lbus_map.write 0x2848 0x00000FFF  #GP3 0x2812 (flush)
     ($cc).proc_lbus_map.write 0x2870 0xB0000000  #SBE Vital 0x281C (load)
     ($cc).proc_lbus_map.write 0x2870 0x90000000  #SBE Vital 0x281C (start)
 }
@@ -49,7 +49,7 @@ foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) {
     ($pnor).sfc_master->regs_ADRCBF = 0x0
     ($pnor).sfc_master->regs_ADRCMF = 0xF
 
-    #Direct Access Cache Disable 
+    #Direct Access Cache Disable
     ($pnor).sfc_master->regs_CONF = 0x00000002
 
     #Small Erase op code
@@ -57,7 +57,7 @@ foreach $pnor in (get-object-list Lpc2SpiFpgaCmp) {
     #Erase Size
     ($pnor).sfc_master->regs_CONF5 = 0x1000
 
-    #Enable 4 byte address mode - must write via memory to trigger 
+    #Enable 4 byte address mode - must write via memory to trigger
     #model behavior
     ($pnor).fsi_local_lbus_map.write 0xC40 0x00006E00
 }