Pick up Simics FSI fixes for multiple chips

Updating the Simics level to get FSI fixes to allow multiple
 chips to work.  This also allows us to remove some previous
 workarounds.
The new Simics build pulled in a different PNOR so needed to
 disable some of the tests.
The new Simics build also modified some of the L3 objects so
 changes were required to some debug tools.
Had to update the VENICE config since Ched rewired it to look
 like MURANO/Tuleta.

Testing:
 Verified 2-proc, 4-centaur MURANO config
 Verified 2-proc, 4-centaur VENICE config

Change-Id: I6aaaf8aad2f82dbfffb8ade551d545bedaa3e048
RTC: 41305
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1066
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

7 files changed, 35 insertions, 30 deletions

diff --git a/src/build/citest/autocitest b/src/build/citest/autocitest
index bd41cfccd..cc49290ea 100755
--- a/src/build/citest/autocitest
+++ b/src/build/citest/autocitest
@@ -107,6 +107,7 @@ fi
 ##  set up
 ##
 DRIVER="$1"                     ##  backing tree
+export bb=$DRIVER               ##  simulate a workon
 TEST_SANDBOX="$2"               ##  test sandbox
 HBICORE_TEST="$3"               ##  path to hbicore_test.img
 
@@ -387,7 +388,7 @@ tracecalls=`cat $SBXHOME/tracecalls.log | xargs echo -n`
 
 
 echo "====> dump printk buffer..."
-autosim $NOWIN --simcmd "memory_image_ln0.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size"  1> /dev/null 2> /dev/null
+autosim $NOWIN --simcmd "p8Proc0.l3_cache_image.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size"  1> /dev/null 2> /dev/null
 if [ $? -ne 0 ] ; then
 echo "ERROR: Unable to run $?"
        stopsim
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
index f832afe05..588c3b8b7 100644
--- a/src/build/citest/etc/bbuild
+++ b/src/build/citest/etc/bbuild
@@ -1 +1 @@
-/esw/fips810/Builds/b0419a_1215.810
+/esw/fips810/Builds/b0510a_1219.810
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 9d27730f7..821b936fa 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -27,7 +27,37 @@
 ##    to setup the sandbox
 ##
 
+#####
 echo "+++ Point Simics to our base image +++"
 #ln -sf $sb/../img/hbicore.bin $sb/../simics/hostboot.bin
 mkdir -p $sb/../images/ppc/lab/flash/
 ln -sf $sb/../img/hbicore.bin $sb/../images/ppc/lab/flash/hostboot.bin
+#####
+
+#####
+#@fixme - Fix with RTC:41342
+echo "+++ Copy centaur.act"
+mkdir -p $sb/simu/data/cec-chip
+cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip/centaur.act
+#####
+
+#####
+#@fixme - Fix with RTC:41342
+echo "+++ Update Model EC."
+mkdir -p $sb/simu/configs/
+
+cp --update $bb/src/simu/configs/P8_MURANO.config $sb/simu/configs/P8_MURANO.config
+sed -i -e's/SETENV GFW_P8_MURANO_PROC_MODEL_EC.*/SETENV GFW_P8_MURANO_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_MURANO.config
+sed -i -e's/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC.*/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC 910610/' $sb/simu/configs/P8_MURANO.config
+
+cp --update $bb/src/simu/configs/P8_VENICE.config $sb/simu/configs/P8_VENICE.config
+sed -i -e's/SETENV GFW_P8_VENICE_PROC_MODEL_EC.*/SETENV GFW_P8_VENICE_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_VENICE.config
+#####
+
+#####
+#@fixme - Fix with RTC:41205
+echo "+++ Fix centaur aliases in p8.act (SW141619) +++"
+mkdir -p $sb/simu/data/cec-chip/
+cp --update $bb/src/simu/data/cec-chip/p8.act $sb/simu/data/cec-chip/
+sed -i -e's/mycentaur/mymcPort/' $sb/simu/data/cec-chip/p8.act
+#####
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 265862240..d8616729f 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -27,28 +27,6 @@
 ##    to setup the sandbox
 ##
 
-echo "+++ Copy centaur.act"
-mkdir -p $sb/simu/data/cec-chip
-cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip/centaur.act
-
-echo "+++ Copy desired config file to sandbox and modify Model EC."
-mkdir -p $sb/simu/configs
-cp --update $BACKING_BUILD/src/simu/configs/P8_MURANO.config $sb/simu/configs
-cp --update $BACKING_BUILD/src/simu/configs/P8_VENICE.config $sb/simu/configs
-sed -i -e's/SETENV GFW_P8_MURANO_PROC_MODEL_EC.*/SETENV GFW_P8_MURANO_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_MURANO.config
-sed -i -e's/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC.*/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC 910610/' $sb/simu/configs/P8_MURANO.config
-sed -i -e's/SETENV GFW_P8_VENICE_PROC_MODEL_EC.*/SETENV GFW_P8_VENICE_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_VENICE.config
-
-echo "+++ Enable 8-threads."
-sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_VENICE.config
-sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_MURANO.config
-
-#Remove with RTC:40975
-echo "+++ Update to new phyp level for XSCOM fixes."
-mkdir -p $sb/simu/data
-cp --update $BACKING_BUILD/src/simu/data/simicsInfo $sb/simu/data/simicsInfo
-sed -i -e's/^WSALIAS DEFAULT PHYPLEVEL.*/WSALIAS DEFAULT PHYPLEVEL env\/phypb\/simics-4.2.0\/simics-4.2.85\/ph120424b700.42/' $sb/simu/data/simicsInfo
-
 
 #### Examples ####
 #echo "+++ Some message about why you need to do this."
diff --git a/src/build/debug/simics-debug-framework.py b/src/build/debug/simics-debug-framework.py
index edf5f0bdd..682c8aa56 100755
--- a/src/build/debug/simics-debug-framework.py
+++ b/src/build/debug/simics-debug-framework.py
@@ -399,7 +399,7 @@ def magic_instruction_callback(user_arg, cpu, arg):
             # fsp-trace style.
             writeLongLong(tracBinaryInfoAddr+8,1)
         # Save the tracBinary buffer to a file named tracBINARY in current dir
-        saveCommand = "memory_image_ln0.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed)
+        saveCommand = "p8Proc0.l3_cache_image.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed)
         SIM_run_alone(run_command, saveCommand )
         # Run fsp-trace on tracBINARY file (implied), append output to tracMERG
         os.system( "fsp-trace ./ -s hbotStringFile >>tracMERG  2>/dev/null" )
diff --git a/src/build/simics/hb-simdebug.py b/src/build/simics/hb-simdebug.py
index 9b779dd67..7041bd2e5 100755
--- a/src/build/simics/hb-simdebug.py
+++ b/src/build/simics/hb-simdebug.py
@@ -44,7 +44,7 @@ def dumpL3():
     #print t
 
     #dump L3 to hbdump.<timestamp>
-    string = "memory_image_ln0.save hbdump.%s 0 0x%x"%(t, L3_SIZE)
+    string = "p8Proc0.l3_cache_image.save hbdump.%s 0 0x%x"%(t, L3_SIZE)
     #print string
     result = run_command(string)
     #print result
diff --git a/src/build/simics/post_model_hook.simics b/src/build/simics/post_model_hook.simics
index f2705f615..656b55b8e 100755
--- a/src/build/simics/post_model_hook.simics
+++ b/src/build/simics/post_model_hook.simics
@@ -49,7 +49,3 @@ venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0140000000     #02010917
 venice_cec_chip_cmp0.psi_hb->psihb_irsn=0x00030000FFFF0000   #0201091b
 p8Proc0.proc_fsi2host_mbox->responder_enable=1
 
-#@fixme - Remove with RTC:41070
-#Get the OCC scoms to work correctly
-p8Proc0.occ_scom_bridge->occ_pib=p8Proc0.OccComplexSlot.OccSimpleSlot.pcb_space
-p8Proc0.OccComplexSlot.OccSimpleSlot.ocb->trusted_boot=FALSE