Add triggerMPIPL simics script into the build directory

This is a handy script that can be used to trigger our standalone model
re-ipl with the MPIPL flag set after completing istep 16.

Change-Id: I270b7a1ec4dbd5a8fe4e2aee69bd55d88c4340f2
RTC: 157653
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30423
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/build/simics/triggerMPIPL.simics b/src/build/simics/triggerMPIPL.simics
new file mode 100644
index 000000000..e026b1319
--- /dev/null
+++ b/src/build/simics/triggerMPIPL.simics
@@ -0,0 +1,30 @@
+#This script is to be ran after IPL Complete has run (after istep16)
+#Run it while simics is at a breakpoint then continue, you should start
+#at the bootloader
+
+#trigger coreReset with fake action/reg
+($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x05000004 "10000000_00000000" 64
+
+#set PPM General Power Management Mode Register to 0
+($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x200f0100 "0x00000000_00000000" 64
+#set actual/required stop states on PPM STOP_STATE_HIST_OTR_REG
+($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x200f0113 "0x2B000000_00000000" 64
+
+
+#set regs on master thread to prepare for bootloader
+($hb_cpu).write-reg IAR 0x3000
+($hb_cpu).write-reg HRMOR 0x8200000
+($hb_cpu).write-reg MSR 0xd000000000000000
+($hb_cpu).write-reg LPCR 0x800040000000800c
+
+#load in the bootloader code
+system_cmp0.phys_mem.load-file ../obj/ppc/hbfw/img/hbbl.bin 0x8203000
+
+#set up memory that SBE usually sets
+system_cmp0.phys_mem.write address = 0x820000c value = 0x0000000000006000 size = 8
+
+#set isMPIPL mode to be true
+($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "20000000_00000000" 64
+
+#start off the master thread
+($hb_cpu).enable