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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2018-06-14 00:35:39 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-18 16:14:58 -0400 |
| commit | 30fe98727be23efd15e10d32167b62aae8bc46d7 (patch) | |
| tree | 2314782022c2b2796479ae9d5333381b6ce06bfd /src/build/citest | |
| parent | 8fcc6813c0987036205079e6db94257687b927a8 (diff) | |
| download | talos-hostboot-30fe98727be23efd15e10d32167b62aae8bc46d7.tar.gz talos-hostboot-30fe98727be23efd15e10d32167b62aae8bc46d7.zip | |
Secure Boot: Centaur Security: Fix handling of 9 Centaur registers
Removed or modified 9 security sensitive Centaur SCOM registers
Change-Id: Iee2e7a08995e2540be477fcea75a4c804422171d
CQ: SW431769
CMVC-Prereq: 1058651
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60534
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest')
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 8444a18ff..74609b755 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -40,3 +40,6 @@ cp $BACKING_BUILD/src/simu/data/cec-chip/p9c.act $sb/simu/data/cec-chip cp $BACKING_BUILD/src/simu/data/cec-chip/p9n.act $sb/simu/data/cec-chip patch -p0 $sb/simu/data/cec-chip/p9c.act $PROJECT_ROOT/src/build/citest/etc/patches/p9c.act.iovalid.patch patch -p0 $sb/simu/data/cec-chip/p9n.act $PROJECT_ROOT/src/build/citest/etc/patches/p9n.act.iovalid.patch + +# Pull in Centaur action file changes to support Centaur security +sbex -t 1058651 |
