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author | Dan Crowell <dcrowell@us.ibm.com> | 2017-04-10 10:02:18 -0500 |
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committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-04-11 16:14:25 -0400 |
commit | f9a4434b9a54ca4355e1c368f91497b629130ad8 (patch) | |
tree | bd7c71dddf5b7954a4c71d589abd7b6bb923ef98 /src/build/citest/etc/workarounds.postsimsetup | |
parent | e9f4e404c176db85b2d4a445cdfe3ddaccad7cfa (diff) | |
download | talos-hostboot-f9a4434b9a54ca4355e1c368f91497b629130ad8.tar.gz talos-hostboot-f9a4434b9a54ca4355e1c368f91497b629130ad8.zip |
Move bbuild to b0404a_1714.910
Remove old workarounds for 1019444,1020522,1020384
Modify SBE start bits for standalone
Change-Id: I29b9572eb6a8ad74612c297e6fffd4691566899f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39044
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/workarounds.postsimsetup')
-rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index fc424a148..5a98fbd80 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -33,18 +33,3 @@ #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File #pull in new actions in p9_memory.act RTC 171066 -echo "+++ Updating p9n_memory.act file for p9_mss_ddr_phy_reset" -sbex -t 1019444 - -#pull in href makefile fix -echo "+++ Updating href makefile" -sbex -t 1020522 - -#pull in new sbe image -echo "+++ Updating sbe image" -sbex -t 1020384 -chmod 777 $sb/sbei/sbfw/img/* -mkdir -p $sb/engd/href/ -cd $sb/engd/href -mk -a -k - |