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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-05-01 14:25:39 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-14 10:51:15 -0400 |
| commit | f9a40964fc9dfe9209ea6da3622f39959dd10477 (patch) | |
| tree | 74966484b5cfb08d309e7d027c3dc240e3df9d72 /src/build/citest/etc/workarounds.postsimsetup | |
| parent | d46f111a8f66830714e32d003982718d13abf66f (diff) | |
| download | talos-hostboot-f9a40964fc9dfe9209ea6da3622f39959dd10477.tar.gz talos-hostboot-f9a40964fc9dfe9209ea6da3622f39959dd10477.zip | |
support IO reconfig loop for OBUS DL link training failures
- p9c DD1.1+ only, DD1.0 not supported
- FW to trigger reconfig loop back to step 0 from
sys_proc_fab_iovalid if:
1) sys_proc_fab_iovalid rc = FAPI2_RC_SUCCESS
-- AND --
2) new output o_obus_dl_rcs (vector of P9_FAB_IOVALID_DL_NOT_TRAINED_ERR rc
objects identifying links which failed on this chip) has entries
- attribute changes:
ATTR_LINK_TRAIN -- remove platinit tag, attr should init to zero (both even
and odd), and reconfig loop will adjust value as we go
CMVC-Prereq:1057645
Change-Id: I95eebd2b893db6d2511aae40798c0a4e049835d6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59022
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59039
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/workarounds.postsimsetup')
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 957d73b8f..deb563d16 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -41,3 +41,10 @@ cd - #grab new action files for Centaur sbex -t 1055588 + +### Update p9c.act and p9n.act for IOVALID HWP change in commit https://ralgit01.raleigh.ibm.com/gerrit1/#/c/59022/ +echo "+++ Updating p9c.act and p9n.act for IOVALID actions +++" +cp $BACKING_BUILD/src/simu/data/cec-chip/p9c.act $sb/simu/data/cec-chip +cp $BACKING_BUILD/src/simu/data/cec-chip/p9n.act $sb/simu/data/cec-chip +patch -p0 $sb/simu/data/cec-chip/p9c.act $PROJECT_ROOT/src/build/citest/etc/patches/p9c.act.iovalid.patch +patch -p0 $sb/simu/data/cec-chip/p9n.act $PROJECT_ROOT/src/build/citest/etc/patches/p9n.act.iovalid.patch |
