support chip swap in memory map via FBC XOR mask programming

p9_sbe_fabricinit.C
p9.fbc.ab_hp.scom.initfile
  set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC
  group/chip ID attribute values, prior to island mode FBC init

  cleanup register/field constant todos

p9_fbc_utils.C
  parametrize p9_fbc_utils_get_chip_base_address to support calculation of
  origin address based on:
    - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS)
    - effective FBC drawer origin -- effective FBC group ID + chip ID=0
      (EFF_FBC_GRP_ID_ONLY)
    - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS)

p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY
  configures BAR address based on drawer base + HRMOR

p9_sbe_load_bootloader.C
  set p9_fbc_utils_get_chip_base_address call for bootloader load to use
  EFF_FBC_GRP_ID_ONLY (drawer)

  store XSCOM/LPC BAR into bootloader config data structure in exception vector
  (based on chip offset)

p9_mss_eff_grouping.C (MCS/HTM BARs)
p9_pcie_config.C (PCIE MMIO BARs)
p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR)
p9_sbe_scominit.C (XSCOM/LPC BARs)
p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs)
  set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox

p9_xip_customize.C
  init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image

Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37777
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 5a98fbd80..7aee7e160 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -33,3 +33,12 @@
 #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
 #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
 #pull in new actions in p9_memory.act RTC 171066
+
+
+#pull in new sbe image
+echo "+++ Updating sbe image"
+sbex -t 1023244
+chmod 777 $sb/sbei/sbfw/img/*
+mkdir -p $sb/engd/href/
+cd $sb/engd/href
+mk -a -k