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| author | Bill Hoffa <wghoffa@us.ibm.com> | 2018-03-20 11:33:42 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-22 12:13:59 -0400 |
| commit | 9de67e525158bdaed7872fe8eb4e9779a18d0f46 (patch) | |
| tree | ac6a94942098053cb683d35a503292010c1775e5 /src/build/citest/etc/workarounds.postsimsetup | |
| parent | 3d7aee811e82959c8f250ce8190ffb739280f6ee (diff) | |
| download | talos-hostboot-9de67e525158bdaed7872fe8eb4e9779a18d0f46.tar.gz talos-hostboot-9de67e525158bdaed7872fe8eb4e9779a18d0f46.zip | |
Update Bbuild to b0316a_1813.920
- Pull in track 1049203 to update to fi180319a900.50 sim model level
Change-Id: I9aa9dff6b8661d9e136afc67339bb882272d5c7f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56083
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/workarounds.postsimsetup')
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index dda3cbfac..eb53ae00f 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -32,8 +32,3 @@ #mkdir -p $sb/simu/data/cec-chip/ #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File - -echo sbex track 1046040 for p9c dd1.1 sbe image -sbex -t 1046040 -cd $sb/sbei/sbfw/img/ -mk -a |
