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authorPrachi Gupta <pragupta@us.ibm.com>2018-02-20 17:12:43 -0600
committerWilliam G. Hoffa <wghoffa@us.ibm.com>2018-02-22 14:20:59 -0500
commit33725d24db91b1877f4c07a004f236f10863bdad (patch)
tree6a22b63ed1155e439667d079d4c6934e72939a5e /src/build/citest/etc/workarounds.postsimsetup
parent0d7e62667706b1c308647133f6fcd0fc974bfb15 (diff)
downloadtalos-hostboot-33725d24db91b1877f4c07a004f236f10863bdad.tar.gz
talos-hostboot-33725d24db91b1877f4c07a004f236f10863bdad.zip
hbfw makefile changes to add p9c dd1.1 sbe to pnor
Change-Id: I592df4c6535a559f226c481cda3da4426bda25d8 CMVC-Prereq:1046040 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54459 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/workarounds.postsimsetup')
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index eb53ae00f..dda3cbfac 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -32,3 +32,8 @@
#mkdir -p $sb/simu/data/cec-chip/
#cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
+
+echo sbex track 1046040 for p9c dd1.1 sbe image
+sbex -t 1046040
+cd $sb/sbei/sbfw/img/
+mk -a
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