Move FSP-only attributes to common targeting for Open Power

- Added default lane masks to Hostboot system XML files
- Added PCIE config related module IDs and reason codes
- Added new packing function to combine 4x uint8 into 1x uint32
- Added dynamic PCIE config for SP-less environments
- Moved PCIE attributes into common attribute definition
- Attached new PCIE attributes to common target definition
- Defaulted PCIE lanes per proc appropriately for all proc chips
- Added CDM_DOMAIN attribute into common attribute definition
- Attached + defaulted CDM domain in common target definition
- Updated common MRW parser to customize the new PCIE attributes

Change-Id: I3779ca6e6a4803d7e78e21e47a92e0b1a09e657d
RTC: 113488
CMVC-coreq: 942076
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13997
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 430 insertions, 3 deletions

diff --git a/src/build/citest/etc/patches/attribute_types.patch b/src/build/citest/etc/patches/attribute_types.patch
index d2cd19443..a97e53b86 100644
--- a/src/build/citest/etc/patches/attribute_types.patch
+++ b/src/build/citest/etc/patches/attribute_types.patch
@@ -1,4 +1,192 @@
-966,984d965
+778,1003c778
+<     <attribute>
+<         <id>IOP_LANES_PER_PROC</id>
+<         <description>Number of PCIE lanes per PROC
+<             creator: MRW
+<             consumer: hwsv
+<             firmware notes:
+<             PCIE Lanes per PROC
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK</id>
+<         <description>PCIE Lane Mask
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask
+<             Array index: IOP number (0:1)
+<                          lane set (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>semi-non-volatile</persistency>
+<         <readable/>
+<         <writeable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_DSMP_CAPABLE</id>
+<         <description>DSMP capability
+<             creator: platform
+<             consumer:
+<             firmware notes:
+<             DSMP capability
+<             Array index: IOP number (0:1)
+<                          Lane Set (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<             </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL</id>
+<         <description>PCIE IOP reversal configuration
+<             creator: HWSV
+<             consumer:
+<             firmware notes:
+<             PCIE IOP reversal configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>semi-non-volatile</persistency>
+<         <readable/>
+<         <writeable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+<         <description>PCIE IOP reversal base configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE IOP reversal base configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+<         <description>PCIE IOP swap base configuration
+<             creator: platform
+<             consumer:
+<             firmware notes:
+<             Encoded PCIE IOP swap configuration
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t></uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+<         <description>PCIE Lane Mask base configuration
+<             creator: HWSV
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask
+<             Array index: IOP number (0:1)
+<                          Lane Index (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<         <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+<         <description>PCIE IOP Reversal bifurcated configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE IOP Reversal bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+<         <description>PCIE IOP swap bifurcated configuration
+<             creator: MRW
+<             consumer:
+<             firmware notes:
+<             Encoded PCIE IOP swap bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t></uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+<         <description>PCIE Lane mask bifurcated configuration
+<             creator: MRW
+<             consumer: 
+<             firmware notes:
+<             PCIE Lane mask bifurcated configuration
+<             Array index: IOP number (0:1)
+<                          Lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint16_t>
+<             </uint16_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+<     <attribute>
 <         <id>PROC_PCIE_LANE_EQUALIZATION</id>
 <         <description>PCIE Lane Equalization values for each PHB
 <             creator: MRW
@@ -18,7 +206,28 @@
 <         <fspOnly/>
 <     </attribute>
 <     <attribute>
-1413,1427d1412
+<         <id>PROC_PCIE_IS_SLOT</id>
+<         <description>Whether the end point is a slot or not
+<             creator:MRW
+<             consumer: 
+<             firmware notes:
+<             Whether the end point is a slot or not
+<             1 - Slot, 0 - not a slot
+<             Array index: Iop Number (0:1)
+<                          lane Set   (0:1)
+<         </description>
+<         <simpleType>
+<             <uint8_t>
+<             </uint8_t>
+<             <array>2,2</array>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <fspOnly/>
+<     </attribute>
+---
+> 
+1413,1427d1187
 <     <attribute>
 <         <id>OCC_MASTER_CAPABLE</id>
 <         <description>
@@ -34,3 +243,69 @@
 <         <readable/>
 <         <fspOnly/>
 <     </attribute>
+1774,1838d1533
+<     <enumerationType>
+<         <id>CDM_DOMAIN</id>
+<         <description>Enumeration indicating CDM Domain of a target</description>
+<         <enumerator>
+<             <name>NONE</name>
+<             <value>0</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>CPU</name>
+<             <value>1</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>DIMM</name>
+<             <value>2</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>FABRIC</name>
+<             <value>3</value>
+<         </enumerator> 
+<         <enumerator>
+<             <name>MEM</name>
+<             <value>4</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>IO</name>
+<             <value>5</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>NODE</name>
+<             <value>6</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>CLOCK</name>
+<             <value>7</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>PSI</name>
+<             <value>8</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>FSP</name>
+<             <value>9</value>
+<         </enumerator>
+<         <enumerator>
+<             <name>ALL</name>
+<             <value>10</value>
+<         </enumerator>
+<         <default>NONE</default>
+<    </enumerationType>
+< 
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <description>Indicates the CDM Domain of an applicable target
+<         </description>
+<         <simpleType>
+<             <enumeration>
+<                 <id>CDM_DOMAIN</id>
+<             </enumeration>
+<         </simpleType>
+<         <persistency>non-volatile</persistency>
+<         <readable/>
+<         <hasStringConversion/>
+<         <fspOnly/>
+<     </attribute>
+<     
diff --git a/src/build/citest/etc/patches/target_types.patch b/src/build/citest/etc/patches/target_types.patch
index 2e53ed871..497d730d8 100644
--- a/src/build/citest/etc/patches/target_types.patch
+++ b/src/build/citest/etc/patches/target_types.patch
@@ -20,7 +20,159 @@
 < </targetType>
 < 
 < <targetType>
-627,629d626
+165,168d143
+<         <id>CDM_DOMAIN</id>
+<         <default>CPU</default>
+<     </attribute>
+<     <attribute>
+356,359d330
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+371,374d341
+<         <id>CDM_DOMAIN</id>
+<         <default>NODE</default>
+<     </attribute>
+<     <attribute>
+596a564
+> 
+600,632d567
+<         <id>PROC_PCIE_LANE_MASK</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_IOP_REVERSAL</id>
+<     </attribute>
+<     <attribute>
+<         <id>PROC_PCIE_DSMP_CAPABLE</id>        
+<     </attribute>
+<     <attribute>
 <         <id>PROC_PCIE_LANE_EQUALIZATION</id>
 <     </attribute>
 <     <attribute>
+<         <id>PROC_PCIE_IS_SLOT</id>
+<     </attribute>
+<     <attribute>
+635,637d569
+<    <attribute>
+<         <id>IOP_LANES_PER_PROC</id>
+<    </attribute>
+643,646d574
+<         <id>IOP_LANES_PER_PROC</id>
+<         <default>24</default>
+<    </attribute>
+<    <attribute>
+659,662d586
+<         <id>IOP_LANES_PER_PROC</id>
+<         <default>32</default>
+<    </attribute>
+<    <attribute>
+702d625
+<  
+734a658
+> 
+881,912d804
+<  
+< <targetTypeExtension>
+<     <id>lcard-dimm</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>DIMM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>chip-processor-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-abus-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-xbus-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+917,920d808
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+<     <attribute>
+925,972d812
+< <targetTypeExtension>
+<     <id>unit-pore-power8</id>
+<     <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>FABRIC</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mbs-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-l4-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mcs-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-mba-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>MEM</default>
+<     </attribute>
+< </targetTypeExtension>
+< 
+< <targetTypeExtension>
+<     <id>unit-pci-power8</id>
+<      <attribute>
+<         <id>CDM_DOMAIN</id>
+<         <default>IO</default>
+<     </attribute>
+< </targetTypeExtension>
+<