TULETA PON - HW procedures update 02/06/2013

Change-Id: I7c2bf13f750920a231e714d0b8068c052d687433
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3110
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

9 files changed, 632 insertions, 515 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index 2e9c55806..5131794f3 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.C,v 1.14 2013/01/28 20:19:06 jaswamin Exp $
+// $Id: io_funcs.C,v 1.15 2013/02/06 09:34:18 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -53,7 +53,6 @@ extern "C"
 /* edi_training.C   - functions of edi_training class                                */
 /****************************************************************************************/
 
-
 //! Wrapper to Run W,D,E,R , F based on bus_status (selected on);
 ReturnCode  edi_training::run_training(const Target& master_target,  io_interface_t master_interface,uint32_t master_group, const Target&  slave_target,  io_interface_t  slave_interface,uint32_t slave_group) {
     ReturnCode rc;
@@ -242,7 +241,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     if (status_data.getHalfWord(0) & fail_bit)
                                     {
                                        FAPI_ERR("io_run_training: the wiretest training state reported a fail  \n");
-				       //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
+				       FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
+				       fapiLogError(rc);
                                        wire_test_status =  FAILED ;
                                        rx_wderf_failed[WIRE_TEST]=true;
                                       // Run First FAILED Data Capture for Wire Test for FAILED bus
@@ -270,7 +270,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                             rx_wderf_failed[DESKEW]=true;
                                             FAPI_ERR("io_run_training : deskew training state reported a fail  \n");
-                                            //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
+                                            FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
+					    fapiLogError(rc);
                                             desckew_status =  FAILED ;
 					    break;
                                     }
@@ -293,7 +294,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     if (status_data.getHalfWord(0) & fail_bit)
                                     {
                                              FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n");
-                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
+                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
+					     fapiLogError(rc);
                                              rx_wderf_failed[EYE_OPT]=true;
                                              eye_opt_status =  FAILED ;
 					     break;
@@ -318,7 +320,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_DBG("io_run_training: static repair encountered an error    \n");
                                              rx_wderf_failed[REPAIR]=true;
-                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
+                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
+					     fapiLogError(rc);
                                              repair_status =  FAILED ;
 					     break;
                                     }
@@ -344,7 +347,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_DBG("io_run_training:   rx_func_mode_failed    \n");
                                              rx_wderf_failed[FUNCTIONAL]=true;
-                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
+                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
+					     fapiLogError(rc);
                                              functional_status =   FAILED ;
 					     break;
                                     }
@@ -365,7 +369,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                         curr_cyc++;
                         FAPI_DBG("\n\t io_run_training: Cycles into polling = %lld\n", curr_cyc);
                         FAPI_DBG("\n\t io_run_training: Cycles remaining in polling = %lld\n", end_cycle - curr_cyc );
-                        rc=fapiDelay(1,increment_poll_cycles);
+			// Updated Loop count and per delay call count to acheive max of 100ms theoretical delay as per Mike Spear 
+                        rc=fapiDelay(1000000,increment_poll_cycles);
                         if(!rc.ok())
                         {
                                FAPI_ERR("io_run_training : Unexpected error in fapiDelay routine\n");
@@ -385,27 +390,32 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
 			    if (wire_test_selected && wire_test_status== RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: wiretest timeout");
-			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
+			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
+			    fapiLogError(rc);
 			    }
 			    else if (desckew_selected && desckew_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: deskew timeout");
-			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
+			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
+			    fapiLogError(rc);
 			    }
 			    else if (repair_selected && repair_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: repair timeout");
-			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
+			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
+			    fapiLogError(rc);
 			    }
 			    else if (eye_opt_selected && eye_opt_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: eyeopt timeout");
-			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
+			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
+			    fapiLogError(rc);
 			    }
 			    else
 			    {
 			    FAPI_ERR("io_run_training: func timeout");
-			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
+			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
+			    fapiLogError(rc);
 			    }
 			    break;
                     }
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
index 6e3883efa..30f538ae0 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.H,v 1.12 2012/12/04 08:28:39 varkeykv Exp $
+// $Id: io_funcs.H,v 1.13 2013/02/06 09:34:19 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -75,8 +75,8 @@ public:
 	bus_status    eye_opt_status;
 	bus_status    repair_status;
 	bus_status    functional_status;
-
-	static const uint32_t      max_poll_cycles=100;
+        //Updating max cycles to suit 100ms theoretical max timeout as per Mike Spear
+	static const uint32_t      max_poll_cycles=100000;
 	static const uint32_t      increment_poll_cycles=1;
 	uint32_t endpoints_set; // How many end points have we accessed so far
 
diff --git a/src/usr/hwpf/hwp/core_activate/core_activate.C b/src/usr/hwpf/hwp/core_activate/core_activate.C
index 6efce283e..6a331112a 100644
--- a/src/usr/hwpf/hwp/core_activate/core_activate.C
+++ b/src/usr/hwpf/hwp/core_activate/core_activate.C
@@ -429,6 +429,9 @@ void*    call_host_ipl_complete( void    *io_pArgs )
 
 
         //  call proc_switch_cfsim
+	// TODO - Comment out to work around Centaur FSI scom issue during BU
+	// RTC 64136 is opened to undo this when in-band scoms are available.
+#if 0
         FAPI_INVOKE_HWP(l_err, proc_switch_cfsim, l_fapi_proc_target,
                         true, // RESET
                         true, // RESET_OPB_SWITCH
@@ -437,6 +440,7 @@ void*    call_host_ipl_complete( void    *io_pArgs )
                         true, // FENCE_PIB_H
                         true, // FENCE_FSI1
                         true); // FENCE_PIB_SW1
+#endif
         if (l_err)
         {
             TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 318592325..d8036a84e 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.50 2013/01/16 20:18:41 jdsloat Exp $
+// $Id: mss_draminit_training.C,v 1.51 2013/01/31 22:33:54 gollub Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.51   | gollub   |31-JAN-13| Uncommenting mss_unmask_draminit_training_errors
 //  1.50   | jdsloat  |16-JAN-13| Fixed rank group enable within PC_INIT_CAL reg
 //  1.49   | jdsloat  |08-JAN-13| Added clearing RD PHASE SELECT values post Read Centering Workaround.
 //  1.48   | jdsloat  |08-JAN-13| Cleared Cal Config in PC_INIT_CAL on opposing port.  
@@ -168,7 +169,7 @@ ReturnCode mss_draminit_training(Target& i_target)
 	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
 	// Else if mss_unmask_draminit_training_errors runs clean, 
 	// it will just return the passed in rc.
-	//l_rc = mss_unmask_draminit_training_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw
+	l_rc = mss_unmask_draminit_training_errors(i_target, l_rc);
 
 	return l_rc;
 }
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
index 4321f9b58..fa924880d 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
@@ -1,481 +1,559 @@
-#-- $Id: cen.dmi.scom.initfile,v 1.6 2012/10/08 20:12:49 bwieman Exp $
-#-- CHANGE HISTORY:
-#--------------------------------------------------------------------------------
-#-- Version:|Author: | Date:  | Comment:
-#-- --------|--------|--------|--------------------------------------------------
-#--     1.4 |thomsen |07/13/12|Updated non-mirrored PRBS_TAP_ID's to have abcdefgabcdefgabc... pattern
-#--     1.3 |jmcgill |06/19/12|Update non-mirrored mode PRBS TX/RX values to make DMI.SETUP_ID = DMI_BUS, setup RX FENCE
-#--     1.2 |thomsen |06/19/12|Updated PRBS_TAP_ID's to match processor
-#--     1.1 |thomsen |06/11/12|Created initial version
-#-- --------|--------|--------|--------------------------------------------------
-#--------------------------------------------------------------------------------
-# End of revision history
-#--------------------------------------------------------------------------------
-
-#--Master list of variables that can be used in this file is at:
-#--<Attribute Definition Location>
+#-- $Id: cen.dmi.scom.initfile,v 1.8 2013/02/04 17:22:52 thomsen Exp $ 
+
+
+####################################################################
+##  
+##  Auto-genrated by fig2scominit.pl
+##      Based on SETUP_ID_MODE DMI_BUS_TR_HW
+##      from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb
+##
+##   Created on Thu Jan 24 14:48:19 EST 2013, by derrin
+####################################################################
+
+## -- CHANGE HISTORY:
+ ## --------------------------------------------------------------------------------
+ ## -- VersionID: |Author:  | Date:  | Comment:
+ ## -- -----------|---------|--------|-------------------------------------------------
+ ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
+ ## -- mbs13011000| mbs     |01-10-13| Added rx_prot_speed_slct and rx_c4_sel
+ ## -- smr12112700| SMR     |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001
+ ## -- jfg12112101| jfg     |11-21-12| Added Zcal inits
+ ## -- jfg12112100| jfg     |11-21-12| Added CU pll modes
+ ## -- 12111300| berger  |11-13-12| Updated with HW eyeopt and recal settings
+ ## -- 12101900| berger  |10-19-12| Updated Z DMI mirror pattern
+ ## -- 12062500| SMR     |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1
+ ## -- 12041000| berger  |04-10-12| Added Z specific settings (scramble tap points, start/end/width id's)
+ ## -- 12021601|mbs      |02-16-12| Broke Centaur rx 6 pack into 4 and 2
+ ## -- 11012500| mbs     |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304
+ ## -- 12011800| RJR     |01-18-12| Added RX_CTL2_REGS FILE REFERENCES           Issue HW164277
+ ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867)
+ ## --         |         |        | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893)
+ ## -- 11120700| mbs     |12-07-11| Fixed RX mirror prbs swizzle for Centaur (HW187542)
+ ## -- 11120500| thomsen |12-05-11| Changed TX.TXCTL.TX_CTL_REGS.base_addr from all 0's to 0x000004.... to set group address to TX
+ ## -- 11111702| jg      |11-17-11| HW184269: Changed swizzle for Centaur
+ ## -- 11102100| SMR     |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register
+ ## -- 11092900| SMR     |09-29-11| HW171978: Added dyn rpr error tallying defaults
+ ## -- 11050300| SMR     |05-02-11| Added tx_max_bad_lanes
+ ## -- 11032200| jg      |02-17-11| Added RX PLLREG register offsets
+ ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodpv_mc_wrap.fig.
+ ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 24 to 17
+ ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass
+ ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings
+ ## -- 11012500| berger  |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields
+ ## -- 11010600| berger  |01-06-11| added lane disable and max bad lane
+ ## -- 11010400| thomsen |01-04-11| Changed TX_BUS_WIDTH from 17 to 24
+ ## -- 10121600| thomsen |12-16-10| Added RX_FENCE
+ ## -- 10121300| thomsen |12-13-10| Swapped DMI_BUS END_LANE_ID values per HW133020
+ ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH and Z support
+ ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX
+ ## -- 10102600| thomsen |10-26-10| Initial version
+ ## --------------------------------------------------------------------------------
+
 
 SyntaxVersion = 1
 
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-#--
-#-- Includes
-#-- Note:  Must include the path to the .define file.
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
+
+
+####################################################################
+#  Define File
+####################################################################
 include edi.io.define
 
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-#--
-#-- Defines
-#--
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-define def_rx_mirrored_mode     = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 1);    # Mirrored mode
-define def_rx_non_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 0);    # Non-Mirrored mode
-define def_tx_mirrored_mode     = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 1);    # Mirrored mode
-define def_tx_non_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 0);    # Non-Mirrored mode
-
-#--******************************************************************************
-#--******************************************************************************
-#-------------------------------------------------------------------------------------
-#    _____      __                 ________
-#   / ___/___  / /___  ______     /  _/ __ \
-#   \__ \/ _ \/ __/ / / / __ \    / // / / /
-#  ___/ /  __/ /_/ /_/ / /_/ /  _/ // /_/ /
-# /____/\___/\__/\__,_/ .___/  /___/_____/   banner2 -fslant
-#                    /_/
-#-------------------------------------------------------------------------------------
-#--******************************************************************************
-# SN bus -> 1 clg, ? lanes
-scom 0x800.0b(rx_id1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,           scom_data;
-        rx_bus_id ,      0b000000;
-        rx_group_id,     0b000000;
-}
-#--******************************************************************************
-scom 0x800.0b(tx_id1_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,           scom_data;
-        tx_bus_id ,      0b000000;
-        tx_group_id,     0b100000; # 0x20
-}
-#--******************************************************************************
-scom 0x800.0b(rx_id2_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                scom_data;
-        rx_last_group_id ,    0b000000;
-}
-#--******************************************************************************
-scom 0x800.0b(tx_id2_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                scom_data;
-        tx_last_group_id,     0b100000;
-}
-#--******************************************************************************
-scom 0x800.0b(rx_id3_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                scom_data;
-        rx_start_lane_id ,    0b0000000;
-        rx_end_lane_id ,      0b0010000;
-}
-#--******************************************************************************
-scom 0x800.0b(tx_id3_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                scom_data;
-        tx_start_lane_id,     0b0000000;
-        tx_end_lane_id ,      0b0010111;
-}
-#--******************************************************************************
-scom 0x800.0b(rx_tx_bus_info_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                scom_data;
-        rx_tx_bus_width ,     0b0011000;
-        rx_rx_bus_width ,     0b0010001;
-}
-#******************************************
-#  .----------------.  .----------------.
-# | .--------------. || .--------------. |
-# | |  _______     | || |  ____  ____  | |
-# | | |_   __ \    | || | |_  _||_  _| | |
-# | |   | |__) |   | || |   \ \  / /   | |
-# | |   |  __ /    | || |    > `' <    | |
-# | |  _| |  \ \_  | || |  _/ /'`\ \_  | |
-# | | |____| |___| | || | |____||____| | |
-# | |              | || |              | |
-# | '--------------' || '--------------' |
-#  '----------------'  '----------------' banner2 -fblock
-#******************************************
-#-------------------------------------------------------------------------------------
-#     ______
-#    / ____/__  ____  ________
-#   / /_  / _ \/ __ \/ ___/ _ \
-#  / __/ /  __/ / / / /__/  __/
-# /_/    \___/_/ /_/\___/\___/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-scom 0x800.0b(rx_fence_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,         scom_data;
-        rx_fence,       0b1;
-}
-#-------------------------------------------------------------------------------------
-#     __  ___           __               __  ___          __
-#    /  |/  /___ ______/ /____  _____   /  |/  /___  ____/ /__
-#   / /|_/ / __ `/ ___/ __/ _ \/ ___/  / /|_/ / __ \/ __  / _ \
-#  / /  / / /_/ (__  ) /_/  __/ /     / /  / / /_/ / /_/ /  __/
-# /_/  /_/\__,_/____/\__/\___/_/     /_/  /_/\____/\__,_/\___/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-#
-scom 0x800.0b(rx_mode_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,           scom_data;
-        rx_master_mode,  0b0;       # Centaur is always a slave
-}
-
-#-------------------------------------------------------------------------------------
-#     ____  __    __
-#    / __ \/ /   / /
-#   / /_/ / /   / /
-#  / ____/ /___/ /___
-# /_/   /_____/_____/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-
-scom 0x800.0b(rx_wiretest_pll_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                              scom_data;
-        rx_wt_cu_pll_reset,                0b1;      # Put PLL in disabled state until Wiretest is started.
-        rx_wt_cu_pll_pgooddly,             0b001;    # 50ns delay
-}
-#-------------------------------------------------------------------------------------
-#     __                        ____  _            __    __         
-#    / /   ____ _____  ___     / __ \(_)________ _/ /_  / /__  _____
-#   / /   / __ `/ __ \/ _ \   / / / / / ___/ __ `/ __ \/ / _ \/ ___/
-#  / /___/ /_/ / / / /  __/  / /_/ / (__  ) /_/ / /_/ / /  __(__  ) 
-# /_____/\__,_/_/ /_/\___/  /_____/_/____/\__,_/_.___/_/\___/____/   banner2 -fslant 
-#-------------------------------------------------------------------------------------
-scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        rx_lane_disabled_vec_0_15,          0b0000000000000000;
-}
-scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-	tx_lane_disabled_vec_0_15,          0b0000000000000000;
-}
-#--******************************************************************************
-scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        rx_lane_disabled_vec_16_31,         0b0111111111111111;
-}
-scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        tx_lane_disabled_vec_16_31,         0b0000000011111111;
-}
-#-------------------------------------------------------------------------------------
-#     __  ___              ____            __   __                         
-#    /  |/  /___ __  __   / __ )____ _____/ /  / /   ____ _____  ___  _____
-#   / /|_/ / __ `/ |/_/  / __  / __ `/ __  /  / /   / __ `/ __ \/ _ \/ ___/
-#  / /  / / /_/ />  <   / /_/ / /_/ / /_/ /  / /___/ /_/ / / / /  __(__  ) 
-# /_/  /_/\__,_/_/|_|  /_____/\__,_/\__,_/  /_____/\__,_/_/ /_/\___/____/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-
-scom 0x800.0b(rx_wiretest_laneinfo_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        rx_wtr_max_bad_lanes,               0b00010;
-}
-#--******************************************************************************
-scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        tx_max_bad_lanes,                   0b00010;
-}
-#-------------------------------------------------------------------------------------
-#     ____                 ____                   _         ______      ____      _            
-#    / __ \__  ______     / __ \___  ____  ____ _(_)____   /_  __/___ _/ / /_  __(_)___  ____ _
-#   / / / / / / / __ \   / /_/ / _ \/ __ \/ __ `/ / ___/    / / / __ `/ / / / / / / __ \/ __ `/
-#  / /_/ / /_/ / / / /  / _, _/  __/ /_/ / /_/ / / /       / / / /_/ / / / /_/ / / / / / /_/ / 
-# /_____/\__, /_/ /_/  /_/ |_|\___/ .___/\__,_/_/_/       /_/  \__,_/_/_/\__, /_/_/ /_/\__, /  
-#       /____/                   /_/                                    /____/        /____/   banner2 -fslant
-#-------------------------------------------------------------------------------------
-scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-	rx_dyn_rpr_bad_lane_max,            0b0001111;
-        rx_dyn_rpr_err_cntr1_duration,      0b0111; 
-        rx_dyn_rpr_enc_bad_data_lane_width, 0b101;
-}
-#--******************************************************************************
-scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits,                               scom_data;
-        rx_dyn_rpr_bad_bus_max,             0b0111111;
-        rx_dyn_rpr_err_cntr2_duration,      0b0111; 
-}
-#-------------------------------------------------------------------------------------
-#     ____  ____  ____ _____    ______               _____      __          __      
-#    / __ \/ __ \/ __ ) ___/   /_  __/___ _____     / ___/___  / /__  _____/ /______
-#   / /_/ / /_/ / __  \__ \     / / / __ `/ __ \    \__ \/ _ \/ / _ \/ ___/ __/ ___/
-#  / ____/ _, _/ /_/ /__/ /    / / / /_/ / /_/ /   ___/ /  __/ /  __/ /__/ /_(__  ) 
-# /_/   /_/ |_/_____/____/    /_/  \__,_/ .___/   /____/\___/_/\___/\___/\__/____/  banner2 -fslant
-#                                      /_/                                      
-#-------------------------------------------------------------------------------------
-# PER-LANE (RX: 17 lanes)
-#-------------------------------------------------------------------------------------
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_0).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_mirrored_mode);     # (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_non_mirrored_mode); # (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_1).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_2).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_3).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_4).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_e,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_e,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_5).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_6).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_7).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_8).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_9).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_10).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_11).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_12).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_e,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_e,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_13).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_d,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_f,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_14).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_c,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_g,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_15).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_b,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_h,        (def_rx_non_mirrored_mode);
-}
-scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0)(lane_16).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_mirrored_mode);
-        rx_prbs_tap_id, rx_prbs_tap_id_pattern_a,        (def_rx_non_mirrored_mode);
-}
-#-------------------------------------------------------------------------------------
-# PER-LANE (TX: 24 lanes)
-#-------------------------------------------------------------------------------------
-# GCR Lane = 0
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 1
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_1).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 2
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_2).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 4
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_3).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 3
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_4).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 5
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_5).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 6
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_6).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 7
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_7).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 8
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_8).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 9
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_9).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 10
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_10).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 11
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 12
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 13
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 14
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 15
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 16
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 17
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 18
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 19
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 20
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_d,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_e,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 21
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_c,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_f,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 22
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_b,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_g,        (def_tx_non_mirrored_mode);
-}
-# GCR Lane = 23
-scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr){
-        bits,           scom_data,                       expr;
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_a,        (def_tx_mirrored_mode);
-        tx_prbs_tap_id, tx_prbs_tap_id_pattern_h,        (def_tx_non_mirrored_mode);
-}
-
-
-#******************************************
-#  .----------------.  .----------------.
-# | .--------------. || .--------------. |
-# | |  _________   | || |  ____  ____  | |
-# | | |  _   _  |  | || | |_  _||_  _| | |
-# | | |_/ | | \_|  | || |   \ \  / /   | |
-# | |     | |      | || |    > `' <    | |
-# | |    _| |_     | || |  _/ /'`\ \_  | |
-# | |   |_____|    | || | |____||____| | |
-# | |              | || |              | |
-# | '--------------' || '--------------' |
-#  '----------------'  '----------------'   banner2 -fblock
-#******************************************
-#-------------------------------------------------------------------------------------
-#     ____       _               __________      ____        __  __
-#    / __ \_____(_)   _____     / ____/ / /__   / __ \____ _/ /_/ /____  _________
-#   / / / / ___/ / | / / _ \   / /   / / //_/  / /_/ / __ `/ __/ __/ _ \/ ___/ __ \
-#  / /_/ / /  / /| |/ /  __/  / /___/ / ,<    / ____/ /_/ / /_/ /_/  __/ /  / / / /
-# /_____/_/  /_/ |___/\___/   \____/_/_/|_|  /_/    \__,_/\__/\__/\___/_/  /_/ /_/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr){
-        bits ,                      scom_data;
-        tx_drv_clk_pattern_gcrmsg,  0b00;        # DRV_0S. Should this be in the scaninit file?
-}
-
-
-############################################################################################
-# END OF FILE
-############################################################################################
+
+#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB
+scom 0x800F1C000201043F { 
+	bits, scom_data, expr;
+	tx_zcal_p_4x, 0b00100, any;
+}
+
+#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB
+scom 0x800F2C000201043F { 
+	bits, scom_data, expr;
+	tx_zcal_sm_max_val, 0b1000110, any;
+	tx_zcal_sm_min_val, 0b0010101, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
+scom 0x800B78000201043F { 
+	bits, scom_data, expr;
+	rx_amin_cfg, 0b111, any;
+	rx_anap_cfg, 0b10, any;
+	rx_h1_cfg, 0b01, any;
+	rx_peak_cfg, 0b10, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
+scom 0x800B80000201043F { 
+	bits, scom_data, expr;
+	rx_ber_cfg, 0b100, any;
+	rx_dac_bo_cfg, 0b100, any;
+	rx_ddc_cfg, 0b10, any;
+	rx_init_tmr_cfg, 0b111, any;
+	rx_prot_cfg, 0b10, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
+scom 0x800A18000201043F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
+scom 0x8009D8000201043F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, any;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, any;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
+scom 0x800AE0000201043F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, any;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
+scom 0x800A38000201043F { 
+	bits, scom_data, expr;
+	rx_eo_enable_ber_test, 0b1, any;
+	rx_eo_enable_ctle_cal, 0b1, any;
+	rx_eo_enable_ddc, 0b1, any;
+	rx_eo_enable_dfe_h1_cal, 0b1, any;
+	rx_eo_enable_final_l2u_adj, 0b1, any;
+	rx_eo_enable_h1ap_tweak, 0b1, any;
+	rx_eo_enable_latch_offset_cal, 0b1, any;
+	rx_eo_enable_result_check, 0b1, any;
+	rx_eo_enable_vga_cal, 0b1, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_FENCE_PG
+scom 0x8009A8000201043F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x800850000201043F { 
+	bits, scom_data, expr;
+	rx_bus_id, 0b000000, any;
+	rx_group_id, 0b000000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_ID2_PG
+scom 0x800858000201043F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_ID3_PG
+scom 0x800860000201043F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010000, any;
+	rx_start_lane_id, 0b0000000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800928000201043F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800930000201043F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0111111111111111, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
+scom 0x8009C0000201043F { 
+	bits, scom_data, expr;
+	rx_c4_sel, 0b00, any;
+	rx_prot_speed_slct, 0b1, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
+scom 0x800AB8000201043F { 
+	bits, scom_data, expr;
+	rx_rc_enable_ber_test, 0b1, any;
+	rx_rc_enable_ctle_cal, 0b1, any;
+	rx_rc_enable_ddc, 0b1, any;
+	rx_rc_enable_dfe_h1_cal, 0b1, any;
+	rx_rc_enable_h1ap_tweak, 0b1, any;
+	rx_rc_enable_latch_offset_cal, 0b1, any;
+	rx_rc_enable_result_check, 0b1, any;
+	rx_rc_enable_vga_cal, 0b1, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP
+scom 0x800B90000201043F { 
+	bits, scom_data, expr;
+	rx_recal_timeout_sel_b, 0b0100, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
+scom 0x800B98000201043F { 
+	bits, scom_data, expr;
+	rx_recal_timeout_sel_h, 0b1011, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
+scom 0x800BA0000201043F { 
+	bits, scom_data, expr;
+	rx_recal_timeout_sel_i, 0b1011, any;
+	rx_recal_timeout_sel_j, 0b1011, any;
+	rx_recal_timeout_sel_k, 0b1011, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_SCOPE_CNTL_PP
+scom 0x800BC0000201043F { 
+	bits, scom_data, expr;
+	rx_scope_control, 0b01, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
+scom 0x800B60000201043F { 
+	bits, scom_data, expr;
+	rx_servo_timeout_sel_b, 0b1000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
+scom 0x800B68000201043F { 
+	bits, scom_data, expr;
+	rx_servo_timeout_sel_h, 0b1011, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
+scom 0x800B70000201043F { 
+	bits, scom_data, expr;
+	rx_servo_timeout_sel_i, 0b1101, any;
+	rx_servo_timeout_sel_j, 0b1101, any;
+	rx_servo_timeout_sel_k, 0b1101, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
+scom 0x800898000201043F { 
+	bits, scom_data, expr;
+	rx_sls_timeout_sel, 0b001, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
+scom 0x800998000201043F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0010001, any;
+	rx_tx_bus_width, 0b0011000, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
+scom 0x800958000201043F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00010, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
+scom 0x800A30000201043F { 
+	bits, scom_data, expr;
+	rx_wt_cu_pll_pgooddly, 0b001, any;
+	rx_wt_cu_pll_reset, 0b0, any;
+}
+
+#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0000201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, any;
+}
+
+#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0010201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, any;
+}
+
+#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0060201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, any;
+}
+
+#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0050201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, any;
+}
+
+#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0040201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, any;
+}
+
+#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0030201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, any;
+}
+
+#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0020201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, any;
+}
+
+#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0070201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, any;
+}
+
+#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0080201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, any;
+}
+
+#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0090201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, any;
+}
+
+#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00E0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, any;
+}
+
+#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00A0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, any;
+}
+
+#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00C0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, any;
+}
+
+#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00D0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, any;
+}
+
+#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00B0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, any;
+}
+
+#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00F0201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, any;
+}
+
+#RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0100201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, any;
+}
+
+#RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B0110201043F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC4000201043F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C94000201043F { 
+	bits, scom_data, expr;
+	tx_bus_id, 0b000000, any;
+	tx_group_id, 0b100000, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_ID2_PG
+scom 0x800C9C000201043F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_ID3_PG
+scom 0x800CA4000201043F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010111, any;
+	tx_start_lane_id, 0b0000000, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800D1C000201043F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800D24000201043F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0000000011111111, any;
+}
+
+#TX.TXCTL.TX_CTL_REGS.TX_MODE_PG
+scom 0x800C1C000201043F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00010, any;
+}
+
+#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434000201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, any;
+}
+
+#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434010201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, any;
+}
+
+#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434020201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, any;
+}
+
+#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434040201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, any;
+}
+
+#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434030201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, any;
+}
+
+#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434050201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, any;
+}
+
+#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434060201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, any;
+}
+
+#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434070201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, any;
+}
+
+#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434080201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, any;
+}
+
+#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434090201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, any;
+}
+
+#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340A0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, any;
+}
+
+#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340B0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, any;
+}
+
+#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340C0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, any;
+}
+
+#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340D0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, any;
+}
+
+#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340E0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, any;
+}
+
+#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340F0201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, any;
+}
+
+#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434100201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, any;
+}
+
+#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434110201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, any;
+}
+
+#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434120201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, any;
+}
+
+#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434130201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, any;
+}
+
+#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434140201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, any;
+}
+
+#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434150201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, any;
+}
+
+#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434160201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, any;
+}
+
+#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x800434170201043F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, any;
+}
 
 
+######################################
+##      END OF FILE
+#######################################
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
index f941f4e8f..ea0df2f1e 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_scominit.C,v 1.3 2013/01/20 19:27:41 jmcgill Exp $
+// $Id: proc_pcie_scominit.C,v 1.4 2013/02/04 23:58:47 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -185,6 +185,9 @@ fapi::ReturnCode proc_pcie_scominit_iop_init(
             rc_ecmd |= gp0_data.writeBit(
                 PCIE_GP0_PHB_IOVALID_BIT[i],
                 phb_active[i]);
+            rc_ecmd |= gp0_data.writeBit(
+                PCIE_GP0_PHB_REFCLOCK_DRIVE_EN_BIT[i],
+                phb_active[i]);
         }
         if (rc_ecmd)
         {
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
index 212ddddad..b829a4439 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_scominit.H,v 1.1 2012/11/05 21:52:43 jmcgill Exp $
+// $Id: proc_pcie_scominit.H,v 1.2 2013/02/04 23:58:46 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -69,6 +69,13 @@ const uint32_t PCIE_GP0_PHB_IOVALID_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] =
     50
 };
 
+const uint32_t PCIE_GP0_PHB_REFCLOCK_DRIVE_EN_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] =
+{
+    52,
+    53,
+    54
+};
+
 // PCIe GP4 register field/bit definitions
 const uint32_t PCIE_GP4_IOP_RESET_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
diff --git a/src/usr/pore/makefile b/src/usr/pore/makefile
index 9ef7025c2..bec883433 100644
--- a/src/usr/pore/makefile
+++ b/src/usr/pore/makefile
@@ -23,5 +23,5 @@
 ROOTPATH = ../../..
 
 SUBDIRS = fapiporeve.d poreve.d test.d
-BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:3a1eb6f314797eccb14376cd368b6b41f070ac4e
+BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:255cc04cd27c64e276c34c38d3ca499d5b195d8b
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 1aac2a445..8488b09b2 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -5588,7 +5588,7 @@ firmware notes: Used as override attribute for pstate procedure
         must track ATTR_CHIP_REGIONS_TO_ENABLE
     </description>
     <simpleType>
-        <uint8_t></uint8_t>
+        <uint8_t><default>1</default></uint8_t>
     </simpleType>
     <persistency>volatile</persistency>
     <readable/>
@@ -9380,19 +9380,22 @@ Measured in GB</description>
     <simpleType>
         <uint8_t>
             <default>
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x20,0x01,0xA0,0x00,0x70,0x00,0x80,0x45,0x45,
-                0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x01,
-                0xA0,0x00,0x70,0x00,0x80,0x45,0x45,0x90,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x20,0x00,0x60,
-                0x00,0x80,0x51,0xA5,0x90,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x80,0x00,0x80,0x01,0xC0,0x00,0x01,
-                0x4B,0x07,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x20,
+		0x00, 0xA0, 0x00, 0x60, 0x01, 0x20, 0x51, 0xBB,
+		0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+		0x20, 0x00, 0xA0, 0x00, 0x60, 0x01, 0x20, 0x51,
+		0xBB, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, 0x80,
+		0x52, 0xC5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x01, 0xC0,
+		0x02, 0x01, 0x4B, 0x17, 0x40, 0x00, 0x00, 0x00, 
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 
             </default>
         </uint8_t>
         <array>128</array>
@@ -9485,8 +9488,8 @@ Measured in GB</description>
                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x44,
                 0x11,0x00,0x00,0x00,0x7e,0x88,0x22,0x00,0x00,0x00,
                 0xfd,0x10,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x10,0x00,0x10,0x00,0x38,0x00,0x00,0x2b,
-                0xa0,0xe8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                0x00,0x00,0x10,0x00,0x10,0x00,0x38,0x00,0x40,0x2b,
+                0xa2,0xe8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
@@ -9532,7 +9535,18 @@ Measured in GB</description>
     </description>
     <simpleType>
         <uint8_t>
-            <default>0</default>
+            <default>
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xAA,
+		0xC3, 0xC0, 0x14, 0x00, 0x00, 0x00, 0x52,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+	    </default>
         </uint8_t>
         <array>80</array>
     </simpleType>
@@ -9610,7 +9624,7 @@ Measured in GB</description>
     </description>
     <simpleType>
         <uint32_t>
-            <default>80</default>
+            <default>0x235</default>
         </uint32_t>
     </simpleType>
     <persistency>non-volatile</persistency>