diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-11-19 07:21:49 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-12-04 16:20:32 -0600 |
| commit | 957f80f13030fb90f6c9f31777d5daf1fed5f050 (patch) | |
| tree | 12e4db0ddad209930073a057f08451c49db0cf3c | |
| parent | 6e21d4f093771dece176d73612ada3769d59f1b3 (diff) | |
| download | talos-hostboot-957f80f13030fb90f6c9f31777d5daf1fed5f050.tar.gz talos-hostboot-957f80f13030fb90f6c9f31777d5daf1fed5f050.zip | |
INITPROC: Hostboot - SW234244 CAPP init update
Change-Id: Icacbf99e52df962d5b287e85af32fb9bb7f3024c
CMVC-Coreq:907021
CQ:SW234244
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7325
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
6 files changed, 336 insertions, 26 deletions
diff --git a/src/build/tools/addCopyright.pl b/src/build/tools/addCopyright.pl index 9b3107c72..d9311d34c 100755 --- a/src/build/tools/addCopyright.pl +++ b/src/build/tools/addCopyright.pl @@ -261,7 +261,7 @@ foreach ( @Files ) ## ## text files are valid, but should generate a warning. - if ("txt" eq $filetype) + if (("txt" eq $filetype) || "Initfile" eq $filetype) { print STDOUT "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"; print STDOUT "WARNING:: File $_ : Filetype: $filetype\n"; @@ -433,6 +433,10 @@ sub filetype { return "txt" } + if ( $filename =~ m/\.initfile$/i ) + { + return "Initfile" + } if ( ( $filename =~ m/\.[cht]$/i ) ||( $filename =~ m/\.[cht]\+\+$/i ) ||( $filename =~ m/\.[cht]pp$/i ) diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index c86d6d1dd..e0d964726 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.164 2013/10/07 14:17:57 jeshua Exp $ +// $Id: p8_scom_addresses.H,v 1.170 2013/11/13 21:21:53 bellows Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -411,6 +411,7 @@ CONST_UINT64_T( OCC_LFIR_MASK_OR_0x01010805 , ULL(0x01010805) ); CONST_UINT64_T( OCC_LFIR_ACT0_0x01010806 , ULL(0x01010806) ); CONST_UINT64_T( OCC_LFIR_ACT1_0x01010807 , ULL(0x01010807) ); +CONST_UINT64_T( OCC_PMC_LFIR_0x01010C00 , ULL(0x01010C00) ); CONST_UINT64_T( OCC_PMC_LFIR_AND_0x01010C01 , ULL(0x01010C01) ); // sram registers @@ -637,6 +638,11 @@ CONST_UINT64_T( LPC_FIR_ACTION0_0x01010C06 , ULL(0x01010C06) ); CONST_UINT64_T( LPC_FIR_ACTION1_0x01010C07 , ULL(0x01010C07) ); //------------------------------------------------------------------------------ +// PCB Master +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCBMS_RESET_REG_0x000F001D , ULL(0x000F001D) ); + +//------------------------------------------------------------------------------ // TP Chiplet PCB slave //------------------------------------------------------------------------------ CONST_UINT64_T( HANG_PULSE_0_REG_0x010F0020 , ULL(0x010F0020) ); @@ -814,12 +820,15 @@ CONST_UINT64_T( PSI_HB_FIR_OR_0x02010902 , ULL(0x02010902) ); //------------------------------------------------------------------------------ // HCA //------------------------------------------------------------------------------ +CONST_UINT64_T( HCA_EN_FIR_0x02010940 , ULL(0x02010940) ); CONST_UINT64_T( HCA_EN_FIR_AND_0x02010941 , ULL(0x02010941) ); CONST_UINT64_T( HCA_EN_BAR_0x0201094A , ULL(0x0201094A) ); CONST_UINT64_T( HCA_EN_MIRROR_BAR_0x02010953 , ULL(0x02010953) ); CONST_UINT64_T( HCA_MODE_0x0201094F , ULL(0x0201094F) ); +CONST_UINT64_T( HCA_EN_EHHCA_FIR_0x02010980 , ULL(0x02010980) ); CONST_UINT64_T( HCA_EN_EHHCA_FIR_AND_0x02010981 , ULL(0x02010981) ); + CONST_UINT64_T( HCA_EH_BAR_0x0201098A , ULL(0x0201098A) ); CONST_UINT64_T( HCA_EH_MIRROR_BAR_0x02010993 , ULL(0x02010993) ); @@ -830,6 +839,7 @@ CONST_UINT64_T( ICP_BAR_0x020109CA , ULL(0x020109CA) ); CONST_UINT64_T( ICP_SYNC_MODE_REG0_0x020109CB , ULL(0x020109CB) ); CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC , ULL(0x020109CC) ); +CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_0x020109C0 , ULL(0x020109C0) ); CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_AND_0x020109C1 , ULL(0x020109C1) ); @@ -873,7 +883,7 @@ CONST_UINT64_T( PB_SCONFIG_LOAD_EAST_0x02010C96 , ULL(0x02010C96) ); // registers without shadow copies // center -CONST_UINT64_T( PB_PMU_0x02010C4F , ULL(0x02010C4F) ); +CONST_UINT64_T( PB_TRACE_0x02010C4F , ULL(0x02010C4F) ); CONST_UINT64_T( PB_NMPM_COUNT_0x02010C50 , ULL(0x02010C50) ); CONST_UINT64_T( PB_LMPM_COUNT_0x02010C51 , ULL(0x02010C51) ); CONST_UINT64_T( PB_RCMD_INTDAT_COUNT_0x02010C52 , ULL(0x02010C52) ); @@ -894,10 +904,11 @@ CONST_UINT64_T( PB_RGP_CMD_RATE_DP_LO_0x02010C64 , ULL(0x02010C64) ); CONST_UINT64_T( PB_RGP_CMD_RATE_DP_HI_0x02010C65 , ULL(0x02010C65) ); CONST_UINT64_T( PB_SP_CMD_RATE_DP_LO_0x02010C66 , ULL(0x02010C66) ); CONST_UINT64_T( PB_SP_CMD_RATE_DP_HI_0x02010C67 , ULL(0x02010C67) ); -CONST_UINT64_T( PB_EVENT_TRACE_0x02010C68 , ULL(0x02010C68) ); -CONST_UINT64_T( PB_EVENT_COMPA_0x02010C69 , ULL(0x02010C69) ); -CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6A , ULL(0x02010C6A) ); -CONST_UINT64_T( PB_CR_ERROR_0x02010C6B , ULL(0x02010C6B) ); +CONST_UINT64_T( PB_PMU_0x02010C68 , ULL(0x02010C68) ); +CONST_UINT64_T( PB_EVENT_SEL_0x02010C69 , ULL(0x02010C69) ); +CONST_UINT64_T( PB_EVENT_COMPA_0x02010C6A , ULL(0x02010C6A) ); +CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6B , ULL(0x02010C6B) ); +CONST_UINT64_T( PB_CR_ERROR_0x02010C6C , ULL(0x02010C6C) ); //------------------------------------------------------------------------------ // NEST PB EH FIR @@ -949,6 +960,7 @@ CONST_UINT64_T( PCBMS_INTERRUPT_TYPE_REG_0x000F001A , ULL(0x000F001A)); //------------------------------------------------------------------------------ CONST_UINT64_T( CAPP_APC_MASTER_PB_CTL_0x02013018 , ULL(0x02013018) ); CONST_UINT64_T( CAPP_CXA_SNOOP_CTL_0x0201301B , ULL(0x0201301B) ); +CONST_UINT64_T( CAPP_APC_MASTER_LCO_TARGET_0x02013021 , ULL(0x02013021) ); //------------------------------------------------------------------------------ // MCS @@ -958,6 +970,8 @@ CONST_UINT64_T( MCS_MCFGPM_0x02011801 , ULL(0x02011801) ); CONST_UINT64_T( MCS_MCFGPR_0x02011802 , ULL(0x02011802) ); CONST_UINT64_T( MCS_MCSMODE0_0x02011807 , ULL(0x02011807) ); CONST_UINT64_T( MCS_MCSMODE1_0x02011808 , ULL(0x02011808) ); +CONST_UINT64_T( MCS_MCSYNC_0x0201180B , ULL(0x0201180B) ); +CONST_UINT64_T( MCS_MODE3_REGISTER_0x0201180A , ULL(0x0201180A) ); CONST_UINT64_T( MCS_MCSMODE4_0x0201181A , ULL(0x0201181A) ); CONST_UINT64_T( MCS_MCFGPA_0x02011814 , ULL(0x02011814) ); CONST_UINT64_T( MCS_MCFGPMA_0x02011815 , ULL(0x02011815) ); @@ -974,12 +988,21 @@ CONST_UINT64_T( MCS_MCIFIRACT1_0x02011847 , ULL(0x02011847) ); CONST_UINT64_T( MCS_MCICFG_0x0201184A , ULL(0x0201184A) ); CONST_UINT64_T( MCS_MCISTAT_0x0201184B , ULL(0x0201184B) ); +CONST_UINT64_T( MCS_MCICRCSYN_0x0201184C , ULL(0x0201184C) ); - +CONST_UINT64_T( MC1_BUSCNTL_FIR_0x02011E00 , ULL(0x02011E00) ); CONST_UINT64_T( MC1_BUSCNTL_FIR_AND_0x02011E01 , ULL(0x02011E01) ); + +CONST_UINT64_T( MC2_MCS0_RIGHT_FIR_0x02011C40 , ULL(0x02011C40) ); CONST_UINT64_T( MC2_MCS0_RIGHT_FIR_AND_0x02011C41 , ULL(0x02011C41) ); + +CONST_UINT64_T( MC2_MCS1_RIGHT_FIR_0x02011CC0 , ULL(0x02011CC0) ); CONST_UINT64_T( MC2_MCS1_RIGHT_FIR_AND_0x02011CC1 , ULL(0x02011CC1) ); + +CONST_UINT64_T( MC3_MCS0_RIGHT_FIR_0x02011D40 , ULL(0x02011D40) ); CONST_UINT64_T( MC3_MCS0_RIGHT_FIR_AND_0x02011D41 , ULL(0x02011D41) ); + +CONST_UINT64_T( MC3_MCS1_RIGHT_FIR_0x02011DC0 , ULL(0x02011DC0) ); CONST_UINT64_T( MC3_MCS1_RIGHT_FIR_AND_0x02011DC1 , ULL(0x02011DC1) ); //------------------------------------------------------------------------------ @@ -1088,9 +1111,16 @@ CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C , ULL(0x0201309C) ); CONST_UINT64_T( NX_CQ_EPS_0x0201309D , ULL(0x0201309D) ); CONST_UINT64_T( NX_AS_MMIO_BAR_0x0201309E , ULL(0x0201309E) ); +CONST_UINT64_T( NX_CAPP_FIR_0x02013000 , ULL(0x02013000) ); CONST_UINT64_T( NX_CAPP_FIR_AND_0x02013001 , ULL(0x02013001) ); + +CONST_UINT64_T( NX_DMA_ENG_FIR_0x02013100 , ULL(0x02013100) ); CONST_UINT64_T( NX_DMA_ENG_FIR_AND_0x02013101 , ULL(0x02013101) ); + +CONST_UINT64_T( NX_CQ_FIR_0x02013080 , ULL(0x02013080) ); CONST_UINT64_T( NX_CQ_FIR_AND_0x02013081 , ULL(0x02013081) ); + +CONST_UINT64_T( NX_AS_FIR_0x020130C0 , ULL(0x020130C0) ); CONST_UINT64_T( NX_AS_FIR_AND_0x020130C1 , ULL(0x020130C1) ); //------------------------------------------------------------------------------ @@ -1203,6 +1233,7 @@ CONST_UINT64_T( X_PERV_LFIR_MASK_OR_0x0404000F , ULL(0x0404000F) ); CONST_UINT64_T( X_PERV_LFIR_ACT0_0x04040010 , ULL(0x04040010) ); CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011 , ULL(0x04040011) ); +CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_0x04011400 , ULL(0x04011400) ); CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_AND_0x04011401 , ULL(0x04011401) ); //------------------------------------------------------------------------------ @@ -1292,6 +1323,7 @@ CONST_UINT64_T( A_PERV_LFIR_MASK_OR_0x0804000F , ULL(0x0804000F) ); CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010 , ULL(0x08040010) ); CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011 , ULL(0x08040011) ); +CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_0x08010C00 , ULL(0x08010C00) ); CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_AND_0x08010C01 , ULL(0x08010C01) ); //------------------------------------------------------------------------------ @@ -1435,6 +1467,7 @@ CONST_UINT64_T( PCIE_PERV_LFIR_MASK_OR_0x0904000F , ULL(0x0904000F) ); CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010 , ULL(0x09040010) ); CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011 , ULL(0x09040011) ); +CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_0x09010800 , ULL(0x09010800) ); CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_AND_0x09010801 , ULL(0x09010801) ); CONST_UINT64_T( PCIE_IOP0_PLL_FIR_0x09011400 , ULL(0x09011400) ); @@ -1986,7 +2019,13 @@ CONST_UINT64_T( WRITE_ALL_HPRE5_0x690F0025 , ULL(0x690F0025) ); CONST_UINT64_T( WRITE_ALL_HPRE6_0x690F0026 , ULL(0x690F0026) ); // hang pulse register 6 CONST_UINT64_T( WRITE_ALL_HPCRE_0x690F0028 , ULL(0x690F0028) ); // hang pulse count register -CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM GP0 initialization +CONST_UINT64_T( READ_GLOBAL_SPATT_FIR_0x570F001A , ULL(0x570F001A) ); // Bitwise read +CONST_UINT64_T( READ_GLOBAL_XSTOP_FIR_0x570F001B , ULL(0x570F001B) ); // Bitwise read +CONST_UINT64_T( READ_GLOBAL_RECOV_FIR_0x570F001C , ULL(0x570F001C) ); // Bitwise read + +CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM G0 initialization + + // other multicast constants were moved to common_scom_addresses.H 1/24/2010 mfred @@ -1999,6 +2038,27 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.170 2013/11/13 21:21:53 bellows +updates for running centaur throttling sync support + +Revision 1.169 2013/11/05 20:29:39 bellows +Added MCS_MCIARCSYN register + +Revision 1.168 2013/10/31 15:36:58 jmcgill +add address for CAPP APC Master LCO Target register + +Revision 1.167 2013/10/21 12:39:19 stillgs + +- Add base FIR registers for reading during MPIPL clear xstop processing +- Add bitwise multicast read addresses for xstop, recoverable and special attention. + Xstop and Recoverable reads used for MPIPL clear xstop + +Revision 1.166 2013/10/17 13:41:10 jmcgill +correct PB PMU register definitions + +Revision 1.165 2013/10/15 16:10:39 jeshua +Added PCBMS_RESET_REG_0x000F001D + Revision 1.164 2013/10/07 14:17:57 jeshua Added some L3 registers and ECID (OTPROM) registers diff --git a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile index c458b4a06..6ee3ca952 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.cxa.scom.initfile,v 1.2 2013/04/08 13:50:19 jmcgill Exp $ +#-- $Id: p8.cxa.scom.initfile,v 1.3 2013/11/09 21:10:48 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -21,6 +21,8 @@ SyntaxVersion = 1 #-------------------------------------------------------------------------------- #-- Defines #-------------------------------------------------------------------------------- +define capp_hang_control_on_scom = (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); +define capp_prod = (ATTR_CHIP_EC_FEATURE_CAPP_PROD != 0); #-------------------------------------------------------------------------------- #-- SCOM initializations @@ -29,18 +31,189 @@ SyntaxVersion = 1 #-- APC Master Config Register scom 0x02013019 { - bits , scom_data, expr; - 4:7 , 0b0000, (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); #-- HANG_POLL_SCALE + bits , scom_data, expr; + 4:7 , 0b0000, (capp_hang_control_on_scom); #-- HANG_POLL_SCALE } #-- CAPP Snoop Control Register scom 0x0201301B { bits , scom_data, expr; - 48:51 , 0b0010, (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); #-- CXA_SNP_DATA_HANG_POLL_SCALE + 45:47 , 0b111, (capp_prod); #-- CXA_SNP_MASTER_ADDRESS_PIPELINE_WAIT_COUNT + 48:51 , 0b0010, (capp_hang_control_on_scom); #-- CXA_SNP_DATA_HANG_POLL_SCALE } #-- CAPP Transport Control Register scom 0x0201301C { bits , scom_data; - 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV + 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV } + +#-- CXA FIR Action0/1 Registers +#-- action0,1 = 00 : checkstop +#-- 01 : recovered attention +#-- 10 : recoverable interrupt +#-- 11 : local checkstop = CAPP Machine Check +scom 0x02013006 { + bits , scom_data; #--Action + 0 , 0b0; #-- 0b00 masked BAR PE + 1 , 0b0; #-- 0b00 xstop Register PE + 2 , 0b0; #-- 0b01 recovered attn Master Array CE + 3 , 0b0; #-- 0b00 xstop Master Array UE + 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b0; #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0; #-- 0b00 xstop Snoop Array UE + 10 , 0b0; #-- 0b00 xstop Recovery Failed + 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0; #-- 0b00 masked Spare + 15 , 0b0; #-- 0b00 masked Scom satellite parity Err + 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0; #-- 0b00 xstop PowerBus parity Err + 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0; #-- 0b00 masked PowerBus Hang Err + 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1; #-- 0b11 capp mach check PHB Link Down + 32 , 0b0; #-- 0b00 masked LD class Foreign Link err + 33 , 0b0; #-- 0b00 masked Foreign Link Hang err + 34 , 0b0; #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0; #-- 0b00 masked XPT PowerBus UE + 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0; #-- 0b00 xstop TLBI Seq Err + 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0; #-- 0b00 masked Spare + 45 , 0b0; #-- 0b00 masked Spare + 46 , 0b0; #-- 0b00 masked Spare + 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 +} +scom 0x02013007 { + bits , scom_data; #--Action + 0 , 0b0; #-- 0b00 masked BAR PE + 1 , 0b0; #-- 0b00 xstop Register PE + 2 , 0b1; #-- 0b01 recovered attn Master Array CE + 3 , 0b0; #-- 0b10 xstop Master Array UE + 4 , 0b1; #-- 0b11 capp mach check Timer Expired Recoverable Epoch + 5 , 0b0; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang + 6 , 0b1; #-- 0b11 capp mach check PSL Cmd UE + 7 , 0b1; #-- 0b11 capp mach check PSL Cmd SUE + 8 , 0b1; #-- 0b01 recovered attn Snoop Array CE + 9 , 0b0; #-- 0b00 xstop Snoop Array UE + 10 , 0b0; #-- 0b00 xstop Recovery Failed + 11 , 0b1; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only + 12 , 0b1; #-- 0b11 capp mach check XPT Recoverable err DD2 only + 13 , 0b1; #-- 0b11 capp mach check Master Recoverable Err + 14 , 0b0; #-- 0b00 masked Spare + 15 , 0b0; #-- 0b00 masked Scom satellite parity Err + 16 , 0b0; #-- 0b00 xstop Master Sys Xstop Err + 17 , 0b0; #-- 0b00 xstop Snooper Sys Xstop Err + 18 , 0b0; #-- 0b00 xstop XPT Sys Xstop Err + 19 , 0b0; #-- 0b00 masked Master Uop Err1 For Lab Use only + 20 , 0b0; #-- 0b00 masked Master Uop Err2 For Lab Use only + 21 , 0b0; #-- 0b00 masked Master Uop Err3 For Lab Use only + 22 , 0b0; #-- 0b00 masked Snooper Uop Err1 For Lab Use only + 23 , 0b0; #-- 0b00 masked Snooper Uop Err2 For Lab Use only + 24 , 0b0; #-- 0b00 masked Snooper Uop Err3 For Lab Use only + 25 , 0b0; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp + 26 , 0b0; #-- 0b00 xstop PowerBus parity Err + 27 , 0b0; #-- 0b00 masked PowerBus Data Hang Err + 28 , 0b0; #-- 0b00 masked PowerBus Hang Err + 29 , 0b0; #-- 0b00 xstop PowerBus Address Err on LD class APC op + 30 , 0b0; #-- 0b00 xstop PowerBus Address Err on ST class APC op + 31 , 0b1; #-- 0b11 capp mach check PHB Link Down + 32 , 0b0; #-- 0b00 masked LD class Foreign Link err + 33 , 0b0; #-- 0b00 masked Foreign Link Hang err + 34 , 0b1; #-- 0b01 recovered attn XPT PowerBus CE + 35 , 0b0; #-- 0b00 masked XPT PowerBus UE + 36 , 0b0; #-- 0b00 masked XPT PowerBus SUE + 37 , 0b1; #-- 0b11 capp mach check TLBI Timeout Err + 38 , 0b0; #-- 0b00 xstop TLBI Seq Err + 39 , 0b0; #-- 0b00 xstop TLBI Bad Op Err + 40 , 0b0; #-- 0b00 xstop TLBI Seq Num Parity Err + 41 , 0b0; #-- 0b00 masked ST class Foreign Link Fail + 42 , 0b0; #-- 0b00 masked TimeBase Err DD2 only + 43 , 0b0; #-- 0b00 masked XPT Informational DD2 only + 44 , 0b0; #-- 0b00 masked Spare + 45 , 0b0; #-- 0b00 masked Spare + 46 , 0b0; #-- 0b00 masked Spare + 47 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 1 + 48 , 0b0; #-- 0b00 masked Scom satellite parity error Copy 2 +} + + +#-- CXA CAPP FIR Mask Register +scom 0x02013003 { + bits , scom_data, expr; + 0 , 0b1, any; #-- BAR PE + 1 , 0b1, (!capp_prod); #-- mask for DD1 Register PE + 1 , 0b0, (capp_prod); #-- Register PE + 2 , 0b0, any; #-- Master Array CE + 3 , 0b0, any; #-- Master Array UE + 4 , 0b0, any; #-- Timer Expired Recoverable Epoch + 5 , 0b0, any; #-- Timer Expired Xstop RCS sequencer hang + 6 , 0b0, any; #-- PSL Cmd UE + 7 , 0b0, any; #-- PSL Cmd SUE + 8 , 0b0, any; #-- Snoop Array CE + 9 , 0b0, any; #-- Snoop Array UE + 10 , 0b0, any; #-- Recovery Failed + 11 , 0b1, (!capp_prod); #-- mask for DD1 Illegal LPC Bar Access DD2 only + 11 , 0b0, (capp_prod); #-- Illegal LPC Bar Access DD2 only + 12 , 0b1, (!capp_prod); #-- mask for DD1 XPT Recoverable err DD2 only + 12 , 0b0, (capp_prod); #-- XPT Recoverable err DD2 only + 13 , 0b0, any; #-- Master Recoverable Err + 14 , 0b1, any; #-- Spare + 15 , 0b1, any; #-- Scom satellite parity Err + 16 , 0b0, any; #-- Master Sys Xstop Err + 17 , 0b0, any; #-- Snooper Sys Xstop Err + 18 , 0b1, (!capp_prod); #-- mask for DD1 XPT Sys Xstop Err + 18 , 0b0, (capp_prod); #-- XPT Sys Xstop Err + 19 , 0b1, any; #-- Master Uop Err1 For Lab Use only + 20 , 0b1, any; #-- Master Uop Err2 For Lab Use only + 21 , 0b1, any; #-- Master Uop Err3 For Lab Use only + 22 , 0b1, any; #-- Snooper Uop Err1 ³or Lab Use only + 23 , 0b1, any; #-- Snooper Uop Err2 ³or Lab Use only + 24 , 0b1, any; #-- Snooper Uop Err3 ³or Lab Use only + 25 , 0b0, any; #-- Unsolicited PowerBus Data or Cresp + 26 , 0b1, (!capp_prod); #-- mask for DD1 PowerBus Parity Err + 26 , 0b0, (capp_prod); #-- PowerBus Parity Err + 27 , 0b1, any; #-- PowerBus Data Hang Err + 28 , 0b1, any; #-- PowerBus Hang Err + 29 , 0b0, any; #-- PowerBus Address Err on LD class APC op + 30 , 0b0, any; #-- PowerBus Address Err on ST class APC op + 31 , 0b0, any; #-- PHB Link Down + 32 , 0b1, any; #-- LD class Foreign Link err + 33 , 0b1, any; #-- Foreign Link Hang err + 34 , 0b0, any; #-- XPT PowerBus CE + 35 , 0b1, any; #-- XPT PowerBus UE + 36 , 0b1, any; #-- XPT PowerBus SUE + 37 , 0b0, any; #-- TLBI Timeout Err + 38 , 0b0, any; #-- TLBI Seq Err + 39 , 0b0, any; #-- TLBI Bad Op Err + 40 , 0b0, any; #-- TLBI Seq Num Parity Err + 41 , 0b1, any; #-- ST class Foreign Link Fail + 42 , 0b1, any; #-- TimeBase Err DD2 only + 43 , 0b1, any; #-- XPT Informational DD2 only + 44 , 0b1, any; #-- Spare + 45 , 0b1, any; #-- Spare + 46 , 0b1, any; #-- Spare + 47 , 0b1, any; #-- Scom satellite parity error Copy 1 + 48 , 0b1, any; #-- Scom satellite parity error Copy 2 +}
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C index ca6859415..13515c50f 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_chiplet_scominit.C,v 1.18 2013/10/28 19:10:50 jmcgill Exp $ +// $Id: proc_chiplet_scominit.C,v 1.22 2013/11/18 14:43:14 thi Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -58,8 +58,12 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) fapi::TargetType target_type; std::vector<fapi::Target> initfile_targets; + std::vector<fapi::Target> ex_targets; + std::vector<fapi::Target> mcs_targets; uint8_t nx_enabled; uint8_t mcs_pos; + uint8_t ex_pos; + uint8_t num_ex_targets; uint8_t master_mcs_pos = 0xFF; fapi::Target master_mcs; uint8_t enable_xbus_resonant_clocking = 0x0; @@ -172,6 +176,65 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) break; } + // configure CXA APC master LCO settings + rc = fapiGetChildChiplets(i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + ex_targets, + fapi::TARGET_STATE_FUNCTIONAL); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets (EX) on %s", + i_target.toEcmdString()); + break; + } + + // form valid LCO target list + for (std::vector<fapi::Target>::iterator i = ex_targets.begin(); + i != ex_targets.end(); + i++) + { + // determine EX chiplet number + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), ex_pos); + + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s", + i->toEcmdString()); + break; + } + + rc_ecmd |= data.setBit(ex_pos-((ex_pos < 8)?(1):(3))); + } + if (!rc.ok()) + { + break; + } + + num_ex_targets = ex_targets.size(); + rc_ecmd |= data.insertFromRight( + num_ex_targets, + CAPP_APC_MASTER_LCO_TARGET_MIN_START_BIT, + (CAPP_APC_MASTER_LCO_TARGET_MIN_END_BIT- + CAPP_APC_MASTER_LCO_TARGET_MIN_START_BIT+1)); + + if (rc_ecmd) + { + FAPI_ERR("proc_chiplet_scominit: Error 0x%x setting APC Master LCO Target register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiPutScom(i_target, + CAPP_APC_MASTER_LCO_TARGET_0x02013021, + data); + if (!rc.ok()) + { + FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (CAPP_APC_MASTER_LCO_TARGET_0x02013021) on %s", + i_target.toEcmdString()); + break; + } + // execute AS SCOM initfile FAPI_INF("proc_chiplet_scominit: Executing %s on %s", PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString()); @@ -200,7 +263,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) enable_xbus_resonant_clocking); if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC"); + FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC on %s", + i_target.toEcmdString()); break; } @@ -212,7 +276,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) data); if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: fapiGetScom error (MBOX_FSIGP6_0x00050015)"); + FAPI_ERR("proc_chiplet_scominit: fapiGetScom error (MBOX_FSIGP6_0x00050015) on %s", + i_target.toEcmdString()); break; } @@ -235,7 +300,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) data); if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (MBOX_FSIGP6_0x00050015)"); + FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (MBOX_FSIGP6_0x00050015) on %s", + i_target.toEcmdString()); break; } } @@ -257,14 +323,14 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) } // determine set of functional MCS chiplets - std::vector<fapi::Target> mcs_targets; rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MCS_CHIPLET, mcs_targets, fapi::TARGET_STATE_FUNCTIONAL); if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets"); + FAPI_ERR("proc_chiplet_scominit: Error from fapiGetChildChiplets (MCS) on %s", + i_target.toEcmdString()); break; } @@ -297,7 +363,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + FAPI_ERR("proc_chiplet_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s", + i->toEcmdString()); break; } @@ -332,6 +399,7 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) { // set MCMODE0Q_ENABLE_CENTAUR_SYNC on first target only // (this bit is required to be set on at most one MCS/chip) + rc_ecmd |= data.flushTo0(); rc_ecmd |= data.setBit(MCSMODE0_EN_CENTAUR_SYNC_BIT); rc_ecmd |= mask.setBit(MCSMODE0_EN_CENTAUR_SYNC_BIT); @@ -351,7 +419,8 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target) mask); if (!rc.ok()) { - FAPI_ERR("proc_chiplet_scominit: fapiPutScomUnderMask error (MCS_MCSMODE0_0x02011807)"); + FAPI_ERR("proc_chiplet_scominit: fapiPutScomUnderMask error (MCS_MCSMODE0_0x02011807) on %s", + master_mcs.toEcmdString()); break; } diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H index 7990f2cd4..3341563c3 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_chiplet_scominit.H,v 1.14 2013/10/28 02:09:55 jmcgill Exp $ +// $Id: proc_chiplet_scominit.H,v 1.15 2013/11/09 21:06:39 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -60,14 +60,19 @@ const char * const PROC_CHIPLET_SCOMINIT_MCS_IF = "p8.mcs.scom.if"; // FSI GP6 Register field/bit definitions -const uint16_t XBUS_RESONANT_CLOCK_CONFIG = 0xF180; - const uint32_t MBOX_FSIGP6_XBUS_RESONANT_CLOCK_CONFIG_START_BIT = 0; const uint32_t MBOX_FSIGP6_XBUS_RESONANT_CLOCK_CONFIG_END_BIT = 15; +const uint16_t XBUS_RESONANT_CLOCK_CONFIG = 0xF180; + // MCS Mode0 Register field/bit definitions const uint32_t MCSMODE0_EN_CENTAUR_SYNC_BIT = 61; +// CAPP APC Master LCO Target Register field/bit definitions +const uint32_t CAPP_APC_MASTER_LCO_TARGET_MIN_START_BIT = 13; +const uint32_t CAPP_APC_MASTER_LCO_TARGET_MIN_END_BIT = 15; + + //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index dc40f492b..db5229ebc 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -12766,5 +12766,4 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> - </attributes> |
