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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-04-19 08:49:45 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-05-19 17:17:12 -0400 |
| commit | 798ff0e50b1dd3a9b0ea640faae67bbd871b909c (patch) | |
| tree | 4cd63b3a941550aef317380feb7bc64ce67b53a4 | |
| parent | 9dd8199cc4169b1e42df37ebdb3f58cc61b1779b (diff) | |
| download | talos-hostboot-798ff0e50b1dd3a9b0ea640faae67bbd871b909c.tar.gz talos-hostboot-798ff0e50b1dd3a9b0ea640faae67bbd871b909c.zip | |
PM reset: Fix disable resclk procedure
CQ:SW427449
Change-Id: I5fa942cc5c4981946a37e3c8b828ff5e12fd16df
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57467
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57475
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C | 43 |
1 files changed, 27 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 9d5110bfd..aa18d12a4 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -753,7 +753,7 @@ fapi2::ReturnCode pm_disable_resclk( CACCR and QACCR don't match"); continue; } - else if(l_caccr_bit_13_14_value) + else if(l_caccr_bit_13_14_value)//if override bit is set { FAPI_INF ("CACCR value %04X", l_caccr_value); @@ -786,18 +786,25 @@ fapi2::ReturnCode pm_disable_resclk( l_step = l_core_index < l_quad_index ? 1 : -1; + l_address = C_CPPM_CACCR; + while (l_core_index != l_quad_index) { l_core_index += l_step; + l_caccr_value = p9_resclk_defines::RESCLK_TABLE_VEC.at(l_core_index); - } - FAPI_INF("Updated CACCR value %04x", l_caccr_value); + FAPI_INF("Updated CACCR value %04x", l_caccr_value); - // Update CACCR (0:11) data - l_core_data64.insert<C_CPPM_CACCR_CLK_SB_STRENGTH, - C_CPPM_CACCR_CLK_SW_SPARE>(l_caccr_value); - l_address = C_CPPM_CACCR; + // Update CACCR (0:11) data + l_core_data64.insert<C_CPPM_CACCR_CLK_SB_STRENGTH, + C_CPPM_CACCR_CLK_SW_SPARE>(l_caccr_value); + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), + "ERROR: Failed to write C_CPPM_CACCR"); + } + + //Clear override bits before QACCR is updated + l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 2>(0); FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), "ERROR: Failed to write C_CPPM_CACCR"); } @@ -806,22 +813,26 @@ fapi2::ReturnCode pm_disable_resclk( //Get power off index value l_poweroff_index = p9_resclk_defines::RESCLK_INDEX_VEC.at(0).idx; + FAPI_INF ("POWER Of index value %u", l_poweroff_index); l_step = l_quad_index < l_poweroff_index ? 1 : -1; + l_address = EQ_QPPM_QACCR; + while (l_poweroff_index != l_quad_index) { l_quad_index += l_step; l_qaccr_value = p9_resclk_defines::RESCLK_TABLE_VEC.at(l_quad_index); - } - FAPI_INF("Updated QACCR value %04x", l_qaccr_value); - // Update QACCR (0:11) data - l_address = EQ_QPPM_QACCR; - l_quad_data64.insert<EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH, - EQ_QPPM_QACCR_COMMON_CLK_SW_SPARE>(l_qaccr_value); - FAPI_TRY(fapi2::putScom(i_target, l_address, l_quad_data64), - "ERROR: Failed to write C_CPPM_CACCR"); + FAPI_INF("Updated QACCR value %04x l_poweroff_index %d l_quad_index %d", l_qaccr_value, + l_poweroff_index, l_quad_index); + + // Update QACCR (0:11) data + l_quad_data64.insert<EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH, + EQ_QPPM_QACCR_COMMON_CLK_SW_SPARE>(l_qaccr_value); + FAPI_TRY(fapi2::putScom(i_target, l_address, l_quad_data64), + "ERROR: Failed to write EQ_QPPM_QACCR"); + } fapi_try_exit: |
