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| author | Andrew Geissler <andrewg@us.ibm.com> | 2016-06-28 08:43:04 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-06-29 11:20:04 -0400 |
| commit | bed9da49a7d63d6f22774c7ff04f2fff0fc4f9ce (patch) | |
| tree | 993196da95ca1859ea1001f6af89fb34347f9659 | |
| parent | 8fd4ede2f56392d3231a2686f40c55a8d2b264d4 (diff) | |
| download | talos-hostboot-bed9da49a7d63d6f22774c7ff04f2fff0fc4f9ce.tar.gz talos-hostboot-bed9da49a7d63d6f22774c7ff04f2fff0fc4f9ce.zip | |
Clear downstream max transfer count register in SBE FIFO
This new register is used to handle FSP to SBE DMA transfers.
Hostboot does not do DMA's but for protocol purposes, we need to
be sure it's set to 0 during our transactions.
Change-Id: I019f3865df670ecea64246e0ec33d488d8acf97c
CQ: SW356256
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26340
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
| -rw-r--r-- | src/usr/sbeio/sbe_fifodd.C | 19 | ||||
| -rw-r--r-- | src/usr/sbeio/sbe_fifodd.H | 1 |
2 files changed, 13 insertions, 7 deletions
diff --git a/src/usr/sbeio/sbe_fifodd.C b/src/usr/sbeio/sbe_fifodd.C index 690ce7743..1b1dfdc21 100644 --- a/src/usr/sbeio/sbe_fifodd.C +++ b/src/usr/sbeio/sbe_fifodd.C @@ -112,9 +112,17 @@ errlHndl_t writeRequest(TARGETING::Target * i_target, do { + // Ensure Downstream Max Transfer Counter is 0 since + // hostboot has no need for it (non-0 can cause + // protocol issues) + uint64_t l_addr = SBE_FIFO_DNFIFO_MAX_TSFR; + uint32_t l_data = 0; + errl = writeFsi(i_target,l_addr,&l_data); + if (errl) break; + //The first uint32_t has the number of uint32_t words in the request + l_addr = SBE_FIFO_UPFIFO_DATA_IN; uint32_t * l_pSent = i_pFifoRequest; //advance as words sent - uint64_t l_addr = SBE_FIFO_UPFIFO_DATA_IN; uint32_t l_cnt = *l_pSent; SBE_TRACDBIN("Write Request in SBEIO",i_pFifoRequest, l_cnt*sizeof(*l_pSent)); @@ -137,7 +145,7 @@ errlHndl_t writeRequest(TARGETING::Target * i_target, if (errl) break; l_addr = SBE_FIFO_UPFIFO_SIG_EOT; - uint32_t l_data = FSB_UPFIFO_SIG_EOT; + l_data = FSB_UPFIFO_SIG_EOT; errl = writeFsi(i_target,l_addr,&l_data); if (errl) break; @@ -254,11 +262,8 @@ errlHndl_t readResponse(TARGETING::Target * i_target, // has been sent. If not EOT, then data ready to receive. uint32_t l_status = 0; errl = waitDnFifoReady(i_target,l_status); - if ( (l_status & DNFIFO_STATUS_DEQUEUED_EOT_FLAG) && - // @TODO-RTC:156194 - EOT should not be set until FIFO empty - // so once fixed, we can remove this next - // line - (!(l_status & DNFIFO_STATUS_FIFO_ENTRY_COUNT)) ) + + if (l_status & DNFIFO_STATUS_DEQUEUED_EOT_FLAG) { l_EOT = true; // ignore EOT dummy word diff --git a/src/usr/sbeio/sbe_fifodd.H b/src/usr/sbeio/sbe_fifodd.H index 4461b558e..e9ccb7e84 100644 --- a/src/usr/sbeio/sbe_fifodd.H +++ b/src/usr/sbeio/sbe_fifodd.H @@ -317,6 +317,7 @@ namespace SBEIO SBE_FIFO_DNFIFO_STATUS = 0x00002444, SBE_FIFO_DNFIFO_RESET = 0x00002450, SBE_FIFO_DNFIFO_ACK_EOT = 0x00002454, + SBE_FIFO_DNFIFO_MAX_TSFR = 0x00002458, }; enum sbeFifoUpstreamStatus |
