summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorcrgeddes <crgeddes@us.ibm.com>2017-03-14 10:18:42 -0500
committerMatthew A. Ploetz <maploetz@us.ibm.com>2017-03-20 17:22:01 -0400
commit579dc1df70c3db1d670c77d267946e09bc8b2cb1 (patch)
tree0acecb4d26993c2d34891ffd891ca3b962d554b2
parented0843d1a2a31368e446f9eddae6e2620262f1fd (diff)
downloadtalos-hostboot-579dc1df70c3db1d670c77d267946e09bc8b2cb1.tar.gz
talos-hostboot-579dc1df70c3db1d670c77d267946e09bc8b2cb1.zip
Deassert PM_EXIT on core0 of both EXs of master EQ
During MPIPL the PM_EXIT bit was being left on the master core. This caused issues when we try to winkle the master core during istep 16.1 Change-Id: I5a74c0cdc0546bc1d973ee4be9496419dd3adc5a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37907 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
-rw-r--r--src/usr/isteps/istep06/host_discover_targets.C20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/usr/isteps/istep06/host_discover_targets.C b/src/usr/isteps/istep06/host_discover_targets.C
index 08b424800..090d64290 100644
--- a/src/usr/isteps/istep06/host_discover_targets.C
+++ b/src/usr/isteps/istep06/host_discover_targets.C
@@ -236,6 +236,9 @@ errlHndl_t powerDownSlaveQuads()
bool l_isMasterEq = false;
TARGETING::TargetHandleList l_eqTargetList;
getAllChiplets(l_eqTargetList, TARGETING::TYPE_EQ, true);
+ uint64_t EX_0_CME_SCOM_SICR_SCOM1 = 0x1001203E;
+ uint64_t CME_SCOM_SICR_PM_EXIT_C0_MASK = 0x0800000000000000;
+ size_t MASK_SIZE = sizeof(CME_SCOM_SICR_PM_EXIT_C0_MASK);
//Need to know who master is so we can skip them
uint8_t l_masterCoreId = TARGETING::getMasterCore()->getAttr<TARGETING::ATTR_CHIP_UNIT>();
@@ -263,6 +266,23 @@ errlHndl_t powerDownSlaveQuads()
//If this is the master quad, we have already power cycled so we dont need this
if(l_isMasterEq)
{
+ //TODO RTC:171340 Need to clear PM_EXIT bit in EX_0_CME_SCOM_SICR_SCOM1 reg for MPIPL
+ //deassert pm exit flag on master core (both ex targs to be safe)
+ TARGETING::TargetHandleList l_exChildren;
+ TARGETING::getChildChiplets( l_exChildren,
+ l_eq_target,
+ TARGETING::TYPE_EX,
+ true);
+
+ for(const auto & l_ex_child : l_exChildren)
+ {
+ // Clear bit 4 of CME_SCOM_SICR which sets PM_EXIT
+ l_err = deviceWrite(l_ex_child,
+ &CME_SCOM_SICR_PM_EXIT_C0_MASK,
+ MASK_SIZE,
+ DEVICE_SCOM_ADDRESS(EX_0_CME_SCOM_SICR_SCOM1)); //0x1001203E
+ }
+ //continue to next EQ
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"Found master, jumping to next EQ");
continue;
OpenPOWER on IntegriCloud