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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-05-23 12:50:06 -0500 |
|---|---|---|
| committer | Dean Sanner <dsanner@us.ibm.com> | 2018-05-23 22:25:53 -0400 |
| commit | 37aa1c9e59194cd97ef0dc4f07d5ec42e34813f6 (patch) | |
| tree | 55ff782fc92b51340fc97d4ef394a42cae1c4aa5 | |
| parent | e9eacec8bad1e2dade70ebed0fc3d00b5ab59232 (diff) | |
| download | talos-hostboot-37aa1c9e59194cd97ef0dc4f07d5ec42e34813f6.tar.gz talos-hostboot-37aa1c9e59194cd97ef0dc4f07d5ec42e34813f6.zip | |
PM_RESCLK: Clear override bits of CACCR in reset flow
Change-Id: I562ebde813ecfd76f7352197276efeccce88b297
CQ:SW430120
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59263
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59272
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Disable-CI: Dean Sanner <dsanner@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index aa18d12a4..8579f3df4 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -569,6 +569,7 @@ fapi2::ReturnCode pm_corequad_reset( uint16_t l_qaccr_value = 0; uint16_t l_caccr_value = 0; l_address = EQ_QPPM_QACCR; + uint8_t l_caccr_bit_13_14_15_value = 0; FAPI_TRY(fapi2::getScom(l_quad_chplt, l_address, l_quad_data64), "ERROR: Failed to read EQ_QPPM_QACCR"); @@ -616,6 +617,21 @@ fapi2::ReturnCode pm_corequad_reset( "CACCR value %04x is not sync with QACCR value %04X", l_caccr_value, l_qaccr_value); } + else + { + //extract 13:14:15 bits + l_core_data64. + extractToRight<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(l_caccr_bit_13_14_15_value); + + if (l_caccr_bit_13_14_15_value) + { + //Clear override bits + l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(0); + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), + "ERROR: Failed to write C_CPPM_CACCR"); + } + + } } } @@ -745,12 +761,11 @@ fapi2::ReturnCode pm_disable_resclk( FAPI_INF("CACCR[0:12] value %04x and CACCR[13:14] %02x", l_caccr_value, l_caccr_bit_13_14_value); - //Compare qaccr and caccr value if ((l_caccr_value != l_qaccr_value) && (!l_caccr_bit_13_14_value)) { FAPI_INF("CME isn't in the middle of things and yet the \ - CACCR and QACCR don't match"); + CACCR and QACCR don't match"); continue; } else if(l_caccr_bit_13_14_value)//if override bit is set @@ -786,7 +801,6 @@ fapi2::ReturnCode pm_disable_resclk( l_step = l_core_index < l_quad_index ? 1 : -1; - l_address = C_CPPM_CACCR; while (l_core_index != l_quad_index) { @@ -802,12 +816,14 @@ fapi2::ReturnCode pm_disable_resclk( FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), "ERROR: Failed to write C_CPPM_CACCR"); } - - //Clear override bits before QACCR is updated - l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 2>(0); - FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), - "ERROR: Failed to write C_CPPM_CACCR"); } + + // By default clear override bits before QACCR is updated + //bit 13:14:15 + l_core_data64.insert<C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE, 3>(0); + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_core_data64), + "ERROR: Failed to write C_CPPM_CACCR"); + } //end of core list } // end of ex list |
