summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorStephen Glancy <sglancy@us.ibm.com>2018-03-19 14:59:14 -0500
committerDean Sanner <dsanner@us.ibm.com>2018-05-25 11:23:06 -0400
commit2254d9f67acf154c5eecda4627f7f9bf1063fe72 (patch)
treea29ce52507a161e97c6e9adace78f5d72d508767
parent90a2cbe1f6071132c390f463d27193d87331a974 (diff)
downloadtalos-hostboot-2254d9f67acf154c5eecda4627f7f9bf1063fe72.tar.gz
talos-hostboot-2254d9f67acf154c5eecda4627f7f9bf1063fe72.zip
Enables DDR4 training advanced
Change-Id: I64a05ce07b8ce734b2269a4218b3c0c06490618e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56452 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56457 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup3
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C5
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H141
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.mk6
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C412
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.mk4
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C183
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H11
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H115
-rw-r--r--src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_address.C40
-rw-r--r--src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C63
-rwxr-xr-xsrc/import/chips/centaur/procedures/hwp/memory/p9c_mss_shmoo_common.H10
-rw-r--r--src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml28
-rw-r--r--src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml21
-rw-r--r--src/usr/isteps/istep13/call_mss_draminit_trainadv.C9
15 files changed, 818 insertions, 233 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 15edd98e5..957d73b8f 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -38,3 +38,6 @@ sbex -t 1051972
cd $sb/sbei/sbfw/
mk -a && mk install_all
cd -
+
+#grab new action files for Centaur
+sbex -t 1055588
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C
index 9974c6c60..e2fe58c4a 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -60,10 +60,9 @@ extern "C" {
start_bit = sb;
num_bits = nb;
}
- PDA_Scom_Storage::~PDA_Scom_Storage() {}
///
- /// @brief PDA_Scom_Storage class constructor
+ /// @brief PDA_MRS_Storage class constructor
/// @param[in] ad Attribute Data
/// @param[in] an Attribute Name
/// @param[in] dr DRAM
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H
index 6392dd533..cc884d770 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -39,57 +39,110 @@
#include <fapi2.H>
#include <vector>
using namespace std;
+
+extern "C"
+{
///
/// @brief PDA MRS storage structure
///
-class PDA_MRS_Storage
-{
- private:
- char pda_string[fapi2::MAX_ECMD_STRING_LEN];
- public:
- uint8_t attribute_data;
- uint32_t attribute_name;
- uint8_t MRS;
- uint8_t dimm;
- uint8_t dram;
- uint8_t rank;
- uint8_t port;
- ///
- /// @brief PDA MRS storage constructor
- ///
- PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di, const uint8_t r,
- const uint8_t p);
- ~PDA_MRS_Storage();
- bool operator> (const PDA_MRS_Storage& PDA2) const;
- bool operator< (const PDA_MRS_Storage& PDA2) const;
- void copy(PDA_MRS_Storage& temp);
- fapi2::ReturnCode setMRSbyAttr(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target);
- fapi2::ReturnCode checkPDAValid(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target);
- char* c_str();
- void generatePDAString();
-};
+ class PDA_MRS_Storage
+ {
+ private:
+ char pda_string[fapi2::MAX_ECMD_STRING_LEN];
+ public:
+ uint8_t attribute_data;
+ uint32_t attribute_name;
+ uint8_t MRS;
+ uint8_t dimm;
+ uint8_t dram;
+ uint8_t rank;
+ uint8_t port;
+
+ ///
+ /// @brief PDA MRS storage constructor
+ /// @param[in] ad attribute data
+ /// @param[in] ad attribute name/ID
+ /// @param[in] dr dram number
+ /// @param[in] di DIMM position
+ /// @param[in] r rank
+ /// @param[in] p port
+ ///
+ PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di, const uint8_t r,
+ const uint8_t p);
+
+ ///
+ /// @brief Destructor
+ ///
+ ~PDA_MRS_Storage();
+
+ ///
+ /// @brief Greater than operator
+ /// @param[in] PDA2 object to compare to
+ /// @return bool true iff this object is greater than the one we're comparing against
+ ///
+ bool operator> (const PDA_MRS_Storage& PDA2) const;
+
+ ///
+ /// @brief Greater than operator
+ /// @param[in] PDA2 object to compare to
+ /// @return bool true iff this object is greater than the one we're comparing against
+ ///
+ bool operator< (const PDA_MRS_Storage& PDA2) const;
+
+ ///
+ /// @brief copies one PDA_MRS_Storage to this one
+ /// @param[in] temp MRS storage data structure
+ ///
+ void copy(PDA_MRS_Storage& temp);
+
+ ///
+ /// @brief sets the MRS variable based upon the inputted attribute name
+ /// @param[in] i_target Centaur MBA target
+ /// @return FAPI2_RC_SUCCESS
+ ///
+ fapi2::ReturnCode setMRSbyAttr(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target);
+
+ ///
+ /// @brief Checks to make sure that
+ /// @param[in] i_target MBA target
+ /// @return FAPI2_RC_SUCCESS iff successful
+ ///
+ fapi2::ReturnCode checkPDAValid(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target);
+
+ ///
+ /// @brief sends out the string
+ /// @return pda string
+ ///
+ char* c_str();
+ void generatePDAString();
+ };
///
/// @brief PDA scom storage structure
///
-class PDA_Scom_Storage
-{
- public:
- uint64_t scom_addr;
- uint32_t start_bit;
- uint32_t num_bits;
- ///
- /// @brief PDA Scom storage constructor
- ///
- PDA_Scom_Storage(const uint64_t sa, const uint32_t sb, const uint32_t nb);
- ~PDA_Scom_Storage();
-};
-
-typedef fapi2::ReturnCode (*mss_ddr4_pda_FP_t)(fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target,
- vector<PDA_MRS_Storage> pda);
+ class PDA_Scom_Storage
+ {
+ public:
+ uint64_t scom_addr;
+ uint32_t start_bit;
+ uint32_t num_bits;
+ ///
+ /// @brief PDA_Scom_Storage constructor
+ /// @param[in] sa Scom Address
+ /// @param[in] sb Start Bit
+ /// @param[in] nb Num Bits
+ ///
+ PDA_Scom_Storage(const uint64_t sa, const uint32_t sb, const uint32_t nb);
+
+ ///
+ /// @brief Default destructor
+ ///
+ ~PDA_Scom_Storage() = default;
+ };
+
+ typedef fapi2::ReturnCode (*mss_ddr4_pda_FP_t)(fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target,
+ vector<PDA_MRS_Storage> pda);
-extern "C"
-{
///
/// @brief runs through the vector of given PDA values and issues the PDA commands to the requested DRAMs
/// @param[in] i_target: Reference to centaur.mba target,
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.mk b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.mk
index 61a02e326..420f67a2e 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.mk
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.mk
@@ -5,7 +5,7 @@
#
# OpenPOWER HostBoot Project
#
-# Contributors Listed Below - COPYRIGHT 2016,2017
+# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
@@ -27,4 +27,8 @@
PROCEDURE=p9c_mss_ddr4_pda
$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE)))
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_mrs6_DDR4
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_access_delay_reg
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_funcs
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_ddr4_funcs
$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C
index b5cd6b0fd..a61b2bb0e 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,14 +27,14 @@
/// @file p9c_mss_draminit_training_advanced.C
/// @brief Tools for centaur procedures
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
-/// *HWP HWP Backup: SARAVANAN SETHURAMAN <saravanans@in.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
+/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
/// *HWP Consumed by: HB:CI
///
-// This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure
+// This procedure Shmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure
// DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation
// DQ & DQS VREF (rd_vref), RCV_IMP shmoo would call rd_eye for margin calculation
// Internal Vref controlled by this function & external vref
@@ -57,9 +57,18 @@
#include <generic/memory/lib/utils/c_str.H>
const uint32_t MASK = 1;
+constexpr uint64_t SAVE_RESTORE_LENGTH = 8;
+enum save_restore_mode : uint8_t
+{
+ SAVE = 0,
+ RESTORE = 1,
+};
+
+constexpr uint64_t REFRESH_BIT = CEN_MBA_MBAREF0Q_CFG_REFRESH_ENABLE;
extern "C"
{
+
///
/// @brief Save and restore registers before and after shmoo
/// @param[in] i_target_mba Centaur input MBA
@@ -81,7 +90,7 @@ extern "C"
const auto l_target_centaur = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
- if(i_mode == 0) // MODE == SAVE
+ if(i_mode == save_restore_mode::SAVE) // MODE == SAVE
{
FAPI_INF("%s: Saving Register contents", mss::c_str(i_target_mba));
@@ -103,7 +112,7 @@ extern "C"
}
}
- else if(i_mode == 1) // MODE == RESTORE
+ else if(i_mode == save_restore_mode::RESTORE) // MODE == RESTORE
{
FAPI_INF("%s: Restoring Register contents", mss::c_str(i_target_mba));
@@ -145,8 +154,198 @@ extern "C"
///
fapi2::ReturnCode p9c_mss_draminit_training_advanced(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba)
{
- FAPI_INF("+++++++ Skipping mss_draminit_training_advanced +++++++");
+ // Define attribute variables
+ uint32_t l_attr_mss_freq_u32 = 0;
+ uint32_t l_attr_mss_volt_u32 = 0;
+ uint8_t l_num_ranks_per_dimm[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {{0}};
+ uint8_t l_port = 0;
+ uint32_t l_left_margin = 0;
+ uint32_t l_right_margin = 0;
+ uint32_t l_shmoo_param = 0;
+ uint8_t l_dram_type = 0;
+ uint8_t l_bin_pda = 0;
+ uint8_t vref_cal_control = 0;
+ uint8_t temp_cal_control = 0;
+ uint32_t l_cal_control[2] = {0};
+ uint64_t l_mcbist_address_config = 0;
+ fapi2::buffer<uint64_t> l_data_buffer_64;
+
+ // Define local variables
+ uint8_t l_shmoo_type_valid_t = 0;
+ uint8_t l_shmoo_param_valid_t = 0;
+ const auto& l_target_centaur = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
+
+ FAPI_INF("%s +++++++ Executing mss_draminit_training_advanced +++++++", mss::c_str(i_target_mba));
+
+ //Save registers pre-shmoo
+ uint64_t i_content_array[SAVE_RESTORE_LENGTH] = {0};
+ FAPI_TRY(mcb_SaveAndRestore(i_target_mba, i_content_array, save_restore_mode::SAVE));
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_FREQ, l_target_centaur, l_attr_mss_freq_u32));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VOLT, l_target_centaur, l_attr_mss_volt_u32));
+ //Preet Add MSS_CAL control here
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VREF_CAL_CNTL, l_target_centaur, vref_cal_control));
+ FAPI_INF("%s +++++++++++ - DDR4 - CAL Control - %d ++++++++++++++++++++", mss::c_str(i_target_mba), vref_cal_control);
+
+
+ //const fapi::Target is centaur.mba
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM, i_target_mba, l_num_ranks_per_dimm));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_GEN, i_target_mba, l_dram_type));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_USER_BANK, i_target_mba, l_bin_pda));
+
+ // Note: the raw 3 below is the result of porting over from the prior product generation - leaving as is as we are unable to track down it's purpose
+ if ((vref_cal_control == fapi2::ENUM_ATTR_CEN_MSS_VREF_CAL_CNTL_DISABLE)
+ && (l_dram_type == fapi2::ENUM_ATTR_CEN_EFF_DRAM_GEN_DDR4) && (l_bin_pda != 3))
+ {
+ FAPI_INF("%s +++++++++++++++++++++++++++++ - DDR4 - Skipping - V-Ref CAL Control +++++++++++++++++++++++++++++++++++++++++++++",
+ mss::c_str(i_target_mba));
+ l_cal_control[0] = mcbist_test_mem::SIMPLE_FIX_RF;
+ l_shmoo_param_valid_t = 1;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_ADDR_MODE, i_target_mba, l_shmoo_param_valid_t));
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_TEST_TYPE, i_target_mba, l_cal_control[0]));
+ FAPI_TRY(wr_vref_shmoo_ddr4_bin(i_target_mba), "Write Vref Shmoo Function Failed");
+
+ // Disable Refresh DDR4 Requirement
+ if (l_dram_type == fapi2::ENUM_ATTR_CEN_EFF_DRAM_GEN_DDR4)
+ {
+ FAPI_INF("%s ************* Disabling Refresh - DDR4 **************", mss::c_str(i_target_mba));
+ FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
+ FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
+ }
+ }
+
+ // Note: the raw 3 below is the result of porting over from the prior product generation - leaving as is as we are unable to track down it's purpose
+ else if ((vref_cal_control != fapi2::ENUM_ATTR_CEN_MSS_VREF_CAL_CNTL_DISABLE)
+ && (l_dram_type == fapi2::ENUM_ATTR_CEN_EFF_DRAM_GEN_DDR4) && (l_bin_pda != 3))
+ {
+ FAPI_INF("%s +++++++++++++++++++++++++++++ - DDR4 - CAL Control +++++++++++ Training ++++++++++++ in Progress ++++++++++++++++",
+ mss::c_str(i_target_mba));
+
+ // Note: cannot be constant'ed due to FAPI_SET_ATTR's macro
+ uint32_t MCBIST_TESTTYPE = mcbist_test_mem::SIMPLE_FIX_RF;
+ constexpr uint64_t MCBIST_START_ADDRESS = 0;
+ constexpr uint64_t SHMOO_MCBIST_END_ADDRESS = 0x0000001fc0000000ull;
+ constexpr uint32_t SHMOO_ALL_VREF = 0xFFFFFFFF;
+
+ // Sets up all of the needed attributes for the shmoo
+ temp_cal_control = fapi2::ENUM_ATTR_CEN_EFF_SCHMOO_PARAM_VALID_WR_VREF;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_PARAM_VALID, i_target_mba, temp_cal_control));
+ temp_cal_control = fapi2::ENUM_ATTR_CEN_EFF_SCHMOO_MODE_QUARTER_CHAR;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_MODE, i_target_mba, temp_cal_control));
+ // Looks like this means we only hit one rank - leaving as this is ported code
+ temp_cal_control = 1;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_USER_BANK, i_target_mba, temp_cal_control));
+ temp_cal_control = fapi2::ENUM_ATTR_CEN_EFF_SCHMOO_TEST_VALID_WR_EYE;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, temp_cal_control));
+ // Looks like this means we only hit one rank - leaving as this is ported code
+ l_shmoo_param_valid_t = 1;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_RANK, i_target_mba, l_shmoo_param_valid_t));
+ l_shmoo_param_valid_t = fapi2::ENUM_ATTR_CEN_EFF_SCHMOO_ADDR_MODE_QUARTER_ADDR;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_ADDR_MODE, i_target_mba, l_shmoo_param_valid_t));
+ l_cal_control[0] = SHMOO_ALL_VREF;
+ l_cal_control[1] = SHMOO_ALL_VREF;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_DRAM_WR_VREF_SCHMOO, i_target_mba, l_cal_control));
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_TEST_TYPE, i_target_mba, MCBIST_TESTTYPE));
+ l_mcbist_address_config = MCBIST_START_ADDRESS;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_START_ADDR, i_target_mba, l_mcbist_address_config));
+ l_mcbist_address_config = SHMOO_MCBIST_END_ADDRESS;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MCBIST_END_ADDR, i_target_mba, l_mcbist_address_config));
+ }
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_USER_BANK, i_target_mba, l_bin_pda));
+
+ FAPI_INF("%s +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++", mss::c_str(i_target_mba));
+ FAPI_INF("%s freq = %d", mss::c_str(i_target_mba), l_attr_mss_freq_u32);
+ FAPI_INF("%s volt = %d", mss::c_str(i_target_mba), l_attr_mss_volt_u32);
+ FAPI_INF("%s num_ranks_per_dimm = [%02d][%02d][%02d][%02d]",
+ mss::c_str(i_target_mba),
+ l_num_ranks_per_dimm[0][0],
+ l_num_ranks_per_dimm[0][1],
+ l_num_ranks_per_dimm[1][0],
+ l_num_ranks_per_dimm[1][1]);
+
+ FAPI_INF("%s +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++", mss::c_str(i_target_mba));
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_shmoo_type_valid_t));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_SCHMOO_PARAM_VALID, i_target_mba, l_shmoo_param_valid_t));
+
+ FAPI_INF("%s +++++++++++++++++++++++++ Read Shmoo Attributes ++++++++++++++++++++++++++", mss::c_str(i_target_mba));
+ FAPI_INF("%s Shmoo param valid = 0x%x", mss::c_str(i_target_mba), l_shmoo_param_valid_t);
+ FAPI_INF("%s Shmoo test valid = 0x%x" , mss::c_str(i_target_mba), l_shmoo_type_valid_t);
+ FAPI_INF("%s +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++", mss::c_str(i_target_mba));
+ //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit
+
+ // Checks to see if we have any ranks - if we do then get to shmooing
+ if ((l_num_ranks_per_dimm[0][0] > 0) ||
+ (l_num_ranks_per_dimm[0][1] > 0) ||
+ (l_num_ranks_per_dimm[1][0] > 0) ||
+ (l_num_ranks_per_dimm[1][1] > 0))
+ {
+ if ((l_shmoo_param_valid_t != PARAM_NONE) ||
+ (l_shmoo_type_valid_t != TEST_NONE))
+ {
+ if ((l_shmoo_param_valid_t& DRV_IMP) != 0)
+ {
+ FAPI_TRY(drv_imped_shmoo(i_target_mba, l_port), "Driver Impedance Shmoo function is Failed");
+ }
+
+ if ((l_shmoo_param_valid_t& SLEW_RATE) != 0)
+ {
+ FAPI_TRY(slew_rate_shmoo(i_target_mba, l_port), "Slew Rate Shmoo Function is Failed");
+ }
+
+ if ((l_shmoo_param_valid_t& WR_VREF) != 0)
+ {
+ if(l_bin_pda == 1)
+ {
+ FAPI_INF("%s ************* Bin - PDA - Vref_Shmoo **************", mss::c_str(i_target_mba));
+
+ FAPI_TRY(wr_vref_shmoo_ddr4_bin(i_target_mba), "Write Vref Shmoo Function is Failed");
+ }
+ else
+ {
+ FAPI_TRY(wr_vref_shmoo_ddr4(i_target_mba), "Write Vref Shmoo Function is Failed");
+ }
+
+ }
+
+ if ((l_shmoo_param_valid_t& RD_VREF) != 0)
+ {
+ FAPI_TRY(rd_vref_shmoo_ddr4(i_target_mba), "Read Vref Shmoo Function Failed");
+ }
+
+ if ((l_shmoo_param_valid_t& RCV_IMP) != 0)
+ {
+ FAPI_TRY(rcv_imp_shmoo(i_target_mba, l_port), "Receiver Impedance Shmoo Function is Failed");
+ }
+
+ if (((l_shmoo_param_valid_t == PARAM_NONE)))
+ {
+ FAPI_TRY(delay_shmoo(i_target_mba, l_port, static_cast<shmoo_type_t>(l_shmoo_type_valid_t),
+ &l_left_margin, &l_right_margin,
+ l_shmoo_param), "Delay Shmoo Function is Failed");
+ }
+ }
+ }
+
+ // Disable Refresh DDR4 Requirement
+ if (l_dram_type == fapi2::ENUM_ATTR_CEN_EFF_DRAM_GEN_DDR4)
+ {
+ FAPI_INF("%s ************* Disabling Refresh - DDR4 **************", mss::c_str(i_target_mba));
+ FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
+ FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
+ }
+
+ // If mss_unmask_draminit_training_advanced_errors gets it's own bad rc,
+ // it will commit the passed in rc (if non-zero), and return it's own bad rc.
+ // Else if mss_unmask_draminit_training_advanced_errors runs clean,
+ // it will just return the passed in rc.
+ FAPI_TRY(mss_unmask_draminit_training_advanced_errors(i_target_mba), "Unmask Function is Failed");
+ FAPI_TRY(mcb_SaveAndRestore(i_target_mba, i_content_array, save_restore_mode::RESTORE));
+fapi_try_exit:
return fapi2::current_err;
}
@@ -165,12 +364,12 @@ fapi2::ReturnCode drv_imped_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
uint8_t l_drv_imp_dq_dqs_nom[MAX_PORTS_PER_MBA] = {0};
uint8_t index = 0;
uint8_t l_slew_rate_dq_dqs[MAX_PORTS_PER_MBA] = {0};
- uint8_t l_slew_rate_dq_dqs_schmoo[MAX_PORTS_PER_MBA] = {0};
- uint32_t l_drv_imp_dq_dqs_schmoo[MAX_PORTS_PER_MBA] = {0};
+ uint8_t l_slew_rate_dq_dqs_shmoo[MAX_PORTS_PER_MBA] = {0};
+ uint32_t l_drv_imp_dq_dqs_shmoo[MAX_PORTS_PER_MBA] = {0};
uint8_t l_drv_imp_dq_dqs_nom_fc = 0;
uint8_t l_drv_imp_dq_dqs_in = 0;
//Temporary
- const shmoo_type_t l_shmoo_type_valid = WR_EYE; //Hard coded, since no other schmoo is applicable for this parameter
+ const shmoo_type_t l_shmoo_type_valid = WR_EYE; //Hard coded, since no other shmoo is applicable for this parameter
uint32_t l_left_margin_drv_imp_array[MAX_DRV_IMP] = {0};
uint32_t l_right_margin_drv_imp_array[MAX_DRV_IMP] = {0};
uint32_t l_left_margin = 0;
@@ -181,29 +380,29 @@ fapi2::ReturnCode drv_imped_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS, i_target_mba, l_slew_rate_dq_dqs));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS, i_target_mba, l_drv_imp_dq_dqs_nom));
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_drv_imp_dq_dqs_schmoo));
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, i_target_mba, l_slew_rate_dq_dqs_schmoo));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_drv_imp_dq_dqs_shmoo));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, i_target_mba, l_slew_rate_dq_dqs_shmoo));
FAPI_INF("+++++++++++++++++Read DRIVER IMP Attributes values++++++++++++++++");
FAPI_INF("CEN_DRV_IMP_DQ_DQS[%d] = [%02d] Ohms, on %s",
i_port,
l_drv_imp_dq_dqs_nom[i_port],
mss::c_str(i_target_mba));
- FAPI_INF("CEN_DRV_IMP_DQ_DQS_SCHMOO[0] = [0x%x], CEN_DRV_IMP_DQ_DQS_SCHMOO[1] = [0x%x] on %s",
- l_drv_imp_dq_dqs_schmoo[0],
- l_drv_imp_dq_dqs_schmoo[1],
+ FAPI_INF("CEN_DRV_IMP_DQ_DQS_SHMOO[0] = [0x%x], CEN_DRV_IMP_DQ_DQS_SHMOO[1] = [0x%x] on %s",
+ l_drv_imp_dq_dqs_shmoo[0],
+ l_drv_imp_dq_dqs_shmoo[1],
mss::c_str(i_target_mba));
FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s",
l_slew_rate_dq_dqs[0],
l_slew_rate_dq_dqs[1],
mss::c_str(i_target_mba));
- FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s",
- l_slew_rate_dq_dqs_schmoo[0],
- l_slew_rate_dq_dqs_schmoo[1],
+ FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SHMOO[1] = [0x%x] on %s",
+ l_slew_rate_dq_dqs_shmoo[0],
+ l_slew_rate_dq_dqs_shmoo[1],
mss::c_str(i_target_mba));
FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
- if(l_drv_imp_dq_dqs_schmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo
+ if(l_drv_imp_dq_dqs_shmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo
{
FAPI_INF("DRIVER IMP Shmoo set to FAST Mode and won't do anything");
}
@@ -211,7 +410,7 @@ fapi2::ReturnCode drv_imped_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
{
for (index = 0; index < MAX_DRV_IMP; index += 1)
{
- if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK)
+ if (l_drv_imp_dq_dqs_shmoo[i_port] & MASK)
{
l_drv_imp_dq_dqs[i_port] = drv_imp_array[index];
FAPI_INF("Current Driver Impedance Value = %d Ohms",
@@ -244,7 +443,7 @@ fapi2::ReturnCode drv_imped_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
l_right_margin_drv_imp_array[index] = 0;
}
- l_drv_imp_dq_dqs_schmoo[i_port] = (l_drv_imp_dq_dqs_schmoo[i_port] >> 1);
+ l_drv_imp_dq_dqs_shmoo[i_port] = (l_drv_imp_dq_dqs_shmoo[i_port] >> 1);
}
l_drv_imp_dq_dqs_nom_fc = l_drv_imp_dq_dqs_nom[i_port];
@@ -290,7 +489,7 @@ fapi2::ReturnCode slew_rate_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
uint8_t l_slew_rate_dq_dqs_nom[MAX_PORTS_PER_MBA] = {0};
uint8_t l_slew_rate_dq_dqs_nom_fc = 0;
uint8_t l_slew_rate_dq_dqs_in = 0;
- uint32_t l_slew_rate_dq_dqs_schmoo[MAX_PORTS_PER_MBA] = {0};
+ uint32_t l_slew_rate_dq_dqs_shmoo[MAX_PORTS_PER_MBA] = {0};
uint8_t l_drv_imp_dq_dqs_nom[MAX_PORTS_PER_MBA] = {0};
const shmoo_type_t l_shmoo_type_valid = WR_EYE; // Hard coded - Other shmoo type is not valid - Temporary
uint8_t count = 0;
@@ -301,9 +500,9 @@ fapi2::ReturnCode slew_rate_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
uint32_t l_right_margin = 0;
uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address
- //Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Schmoo'ed
+ //Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Shmoo'ed
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS, i_target_mba, l_slew_rate_dq_dqs_nom));
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_slew_rate_dq_dqs_schmoo));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_slew_rate_dq_dqs_shmoo));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS, i_target_mba, l_drv_imp_dq_dqs_nom));
FAPI_INF("+++++++++++++++++Read Slew Shmoo Attributes values+++++++++++++++");
@@ -315,13 +514,13 @@ fapi2::ReturnCode slew_rate_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
l_slew_rate_dq_dqs_nom[0],
l_slew_rate_dq_dqs_nom[1],
mss::c_str(i_target_mba));
- FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s",
- l_slew_rate_dq_dqs_schmoo[0],
- l_slew_rate_dq_dqs_schmoo[1],
+ FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SHMOO[1] = [0x%x] on %s",
+ l_slew_rate_dq_dqs_shmoo[0],
+ l_slew_rate_dq_dqs_shmoo[1],
mss::c_str(i_target_mba));
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
- if(l_slew_rate_dq_dqs_schmoo == 0) //Check for any of the bits enabled in the shmoo
+ if(l_slew_rate_dq_dqs_shmoo == 0) //Check for any of the bits enabled in the shmoo
{
FAPI_INF("Slew Rate Shmoo set to FAST Mode and won't do anything");
}
@@ -329,7 +528,7 @@ fapi2::ReturnCode slew_rate_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
{
for (uint8_t index = 0; index < MAX_NUM_SLEW_RATES; index += 1)
{
- if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK)
+ if (l_slew_rate_dq_dqs_shmoo[i_port] & MASK)
{
l_slew_rate_dq_dqs[i_port] = slew_rate_array[index];
FAPI_INF("Current Slew rate value is %d V/ns",
@@ -360,8 +559,8 @@ fapi2::ReturnCode slew_rate_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i
l_right_margin_slew_array[index] = 0;
}
- l_slew_rate_dq_dqs_schmoo[i_port]
- = (l_slew_rate_dq_dqs_schmoo[i_port] >> 1);
+ l_slew_rate_dq_dqs_shmoo[i_port]
+ = (l_slew_rate_dq_dqs_shmoo[i_port] >> 1);
} // end for index
l_slew_rate_dq_dqs_nom_fc = l_slew_rate_dq_dqs_nom[i_port];
@@ -408,10 +607,10 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
uint8_t l_attr_eff_dimm_type_u8 = 0;
uint8_t num_ranks_per_dimm[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
uint8_t l_MAX_RANKS[MAX_DIMM_PER_PORT] = {0};
- uint8_t l_SCHMOO_NIBBLES = 20;
+ uint8_t l_SHMOO_NIBBLES = 20;
uint32_t base_percent = 60000;
uint32_t index_mul_print = 650;
- uint8_t l_attr_schmoo_test_type_u8 = 1;
+ uint8_t l_attr_shmoo_test_type_u8 = 1;
uint32_t vref_val_print = 0;
uint8_t vrefdq_train_range[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t vrefdq_train_value[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
@@ -423,7 +622,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CUSTOM_DIMM, i_target_mba, l_attr_eff_dimm_type_u8));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM, i_target_mba, num_ranks_per_dimm));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_RANGE, i_target_mba, vrefdq_train_range));
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
if(vrefdq_train_range[0][0][0] == 1)
{
@@ -435,14 +634,14 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
if ( l_attr_eff_dimm_type_u8 == fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES )
{
- l_SCHMOO_NIBBLES = 20;
+ l_SHMOO_NIBBLES = 20;
}
else
{
- l_SCHMOO_NIBBLES = 18;
+ l_SHMOO_NIBBLES = 18;
}
- FAPI_DBG(" +++ l_SCHMOO_NIBBLES = %d +++ ", l_SCHMOO_NIBBLES);
+ FAPI_DBG(" +++ l_SHMOO_NIBBLES = %d +++ ", l_SHMOO_NIBBLES);
///// ddr4 vref //////
FAPI_DBG("+++++++++++++++++++++++++++++++++++++++++++++ Patch - WR_VREF - Check Sanity only at 500 ddr4 +++++++++++++++++++++++++++");
FAPI_TRY(delay_shmoo_ddr4(i_target_mba, i_port, l_shmoo_type_valid,
@@ -453,8 +652,8 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
FAPI_TRY(set_attribute(i_target_mba));
l_shmoo_type_valid = WR_EYE;
- l_attr_schmoo_test_type_u8 = 2;
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ l_attr_shmoo_test_type_u8 = 2;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
//Initialize all to zero
for(l_vref_num = 0; l_vref_num < max_ddr4_vrefs1; l_vref_num++)
@@ -463,7 +662,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
vref_val_print = base_percent + (l_vref_num * index_mul_print);
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.clearBit<0>();
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
FAPI_INF("\n After Clearing Refresh");
@@ -514,7 +713,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
FAPI_TRY(p9c_mss_mrs6_DDR4(i_target_mba));
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.setBit<0>();
+ l_data_buffer_64.setBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
FAPI_TRY(delay_shmoo_ddr4(i_target_mba, i_port, l_shmoo_type_valid,
@@ -543,7 +742,7 @@ fapi2::ReturnCode latch_mrs6_val(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_
uint8_t vrefdq_train_enable[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t latch_values[3] = {fapi2::ENUM_ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE_ENABLE, fapi2::ENUM_ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE_ENABLE, fapi2::ENUM_ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE_DISABLE};
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.clearBit<0>();
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
for(uint8_t latch_val = 0; latch_val < 3; latch_val++)
@@ -564,7 +763,7 @@ fapi2::ReturnCode latch_mrs6_val(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_
}
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.setBit<0>();
+ l_data_buffer_64.setBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
fapi_try_exit:
@@ -614,7 +813,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
vector<PDA_MRS_Storage> pda;
pda.clear();
uint32_t index_mul_print = 650;
- uint8_t l_attr_schmoo_test_type_u8 = 1;
+ uint8_t l_attr_shmoo_test_type_u8 = 1;
uint32_t vref_val_print = 0;
uint8_t vpd_wr_vref_value[2] = {0};
const auto l_target_centaur1 = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
@@ -623,7 +822,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CUSTOM_DIMM, i_target_mba, l_attr_eff_dimm_type_u8));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target_mba, num_ranks_per_dimm));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_RANGE, i_target_mba, vrefdq_train_range));
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_DRAM_WRDDR4_VREF, i_target_mba, vpd_wr_vref_value));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VREF_CAL_CNTL, l_target_centaur1, cal_control));
//FAPI_INF("++++++++++++++ATTR_CEN_MSS_VREF_CAL_CNTL = %d +++++++++++++++++++++++++++",cal_control);
@@ -633,26 +832,30 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
base_percent = 45;
}
- FAPI_INF("Setting MCBIST DONE bit MASK as FW reports FIR bits!...");
+ FAPI_INF("%s Setting MCBIST DONE bit MASK as FW reports FIR bits!...", mss::c_str(i_target_mba));
//Workaround MCBIST MASK Bit as FW reports FIR bits --- > SET
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBSPAMSKQ, l_data_buffer_64));
FAPI_TRY(l_data_buffer_64.setBit(10), "Buffer error in function wr_vref_shmoo_ddr4_bin Workaround MCBIST MASK Bit");
- FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ WR_VREF - Check Sanity only MCBIST +++++++++++++++++++++++++++");
+ FAPI_INF("%s +++++++++++++++++++++++++++++++++++++++++++++ WR_VREF - Check Sanity only MCBIST +++++++++++++++++++++++++++",
+ mss::c_str(i_target_mba));
FAPI_TRY(delay_shmoo_ddr4_pda(i_target_mba, l_port, l_shmoo_type_valid,
&l_left_margin, &l_right_margin,
vref_val, pda_nibble_table));
- FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
+ FAPI_INF("%s Setup and Sanity - Check disabled from now on..... Continuing .....", mss::c_str(i_target_mba));
FAPI_TRY(set_attribute(i_target_mba));
- if(cal_control == 3)
+ if(cal_control == fapi2::ENUM_ATTR_CEN_MSS_VREF_CAL_CNTL_BOX)
{
+ constexpr uint8_t WR_VREF_RANGE_MAX = 0x32;
+ constexpr uint8_t WR_VREF_RANGE_MIN = 0x00;
+
l_shmoo_type_valid = BOX;
- FAPI_INF("Running cal control 3 - box shmoo!!!");
- l_attr_schmoo_test_type_u8 = 0x20;
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ FAPI_INF("%s Running box shmoo!!!", mss::c_str(i_target_mba));
+ l_attr_shmoo_test_type_u8 = fapi2::ENUM_ATTR_CEN_EFF_SCHMOO_TEST_VALID_BOX;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, i_target_mba, vrefdq_train_value));
uint8_t vrefdq_train_value_plus[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
uint8_t vrefdq_train_value_minus[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0};
@@ -672,15 +875,15 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
vrefdq_train_value[l_port_index][l_dimm_index][l_rank_index] + vref_train_step_size;
//if over the max, then set to max val
- if(vrefdq_train_value_plus[l_port_index][l_dimm_index][l_rank_index] > 0x32)
+ if(vrefdq_train_value_plus[l_port_index][l_dimm_index][l_rank_index] > WR_VREF_RANGE_MAX)
{
- vrefdq_train_value_plus[l_port_index][l_dimm_index][l_rank_index] = 0x32;
+ vrefdq_train_value_plus[l_port_index][l_dimm_index][l_rank_index] = WR_VREF_RANGE_MAX;
}
//sets up -5%
if(vrefdq_train_value[l_port_index][l_dimm_index][l_rank_index] < vref_train_step_size)
{
- vrefdq_train_value_minus[l_port_index][l_dimm_index][l_rank_index] = 0x00;
+ vrefdq_train_value_minus[l_port_index][l_dimm_index][l_rank_index] = WR_VREF_RANGE_MIN;
}
else
{
@@ -698,26 +901,30 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
FAPI_TRY(delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid,
&l_left_margin, &l_right_margin,
(uint32_t)vref_train_step_size));
+ FAPI_INF("%s found a left margin %lu and a right margin %lu at +VREF %u", mss::c_str(i_target_mba), l_left_margin,
+ l_right_margin, vref_train_step_size);
FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, i_target_mba, vrefdq_train_value_plus));
FAPI_TRY(latch_mrs6_val(i_target_mba));
//should run MCBIST +% VREF +/-X ticks write delay
-
FAPI_TRY(delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid,
&l_left_margin, &l_right_margin,
(uint32_t)(0xff - vref_train_step_size)));
+ FAPI_INF("%s found a left margin %lu and a right margin %lu at -VREF", mss::c_str(i_target_mba), l_left_margin,
+ l_right_margin);
FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, i_target_mba, vrefdq_train_value));
FAPI_TRY(latch_mrs6_val(i_target_mba));
+ FAPI_INF("%s finished with the box shmoo", mss::c_str(i_target_mba));
}
- else if (cal_control != 0)
+ else if (cal_control != fapi2::ENUM_ATTR_CEN_MSS_VREF_CAL_CNTL_DISABLE)
{
l_shmoo_type_valid = WR_EYE;
- l_attr_schmoo_test_type_u8 = 2;
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ l_attr_shmoo_test_type_u8 = 2;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
//Initialise All to Zero [MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM]
for(l_port_index = 0; l_port_index < MAX_PORTS_PER_MBA; l_port_index++) // port
@@ -752,9 +959,10 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
vref_val = l_vref_mid;
vref_val_print = base_percent + (l_vref_mid * index_mul_print);
- FAPI_INF("The Vref value is = %d; The percent voltage bump = %d ", vref_val, vref_val_print);
+ FAPI_INF("%sThe Vref value is = %d; The percent voltage bump = %d ", mss::c_str(i_target_mba), vref_val,
+ vref_val_print);
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.clearBit<0>();
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
for(l_port_index = 0; l_port_index < MAX_PORTS_PER_MBA; l_port_index++)
@@ -806,7 +1014,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
FAPI_TRY(p9c_mss_mrs6_DDR4(i_target_mba), "mrs_load failed");
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.setBit<0>();
+ l_data_buffer_64.setBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
@@ -862,14 +1070,14 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
// What do we do Once we know best V-Ref
FAPI_TRY(fapi2::getScom( i_target_mba, CEN_MBA_MBAREF0Q, refresh_reg));
- refresh_reg.clearBit<0>();
+ refresh_reg.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom( i_target_mba, CEN_MBA_MBAREF0Q, refresh_reg));
if(cal_control == 2)
{
- FAPI_INF("CAL_CONTROL in RANK_Wise Mode!! ");
+ FAPI_INF("%s CAL_CONTROL in RANK_Wise Mode!! ", mss::c_str(i_target_mba));
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.clearBit<0>();
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
for(l_port_index = 0; l_port_index < MAX_PORTS_PER_MBA; l_port_index++)
@@ -947,7 +1155,8 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
{
for(l_nibble_index = 0; l_nibble_index < (DATA_BYTES_PER_PORT * MAX_NIBBLES_PER_BYTE); l_nibble_index++)
{
- FAPI_INF("\n Port %d Dimm %d Rank:%d Pda_Nibble: %d V-ref:%d Margin:%d", l_port_index, l_dimm_index, l_rank_index,
+ FAPI_INF("%s Port %d Dimm %d Rank:%d Pda_Nibble: %d V-ref:%d Margin:%d", mss::c_str(i_target_mba), l_port_index,
+ l_dimm_index, l_rank_index,
l_nibble_index,
best_pda_nibble_table[l_port_index][l_dimm_index][l_rank_index][l_nibble_index][0],
best_pda_nibble_table[l_port_index][l_dimm_index][l_rank_index][l_nibble_index][1]);
@@ -964,17 +1173,18 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
max_vref = max_vref / MAX_NIBBLES_PER_BYTE;
}
- FAPI_INF("\n Port %d Dimm %d Rank:%d Pda_Nibble: %d DRAM_num %d V-ref:%d Margin:%d", l_port_index, l_dimm_index,
+ FAPI_INF("%s Port %d Dimm %d Rank:%d Pda_Nibble: %d DRAM_num %d V-ref:%d Margin:%d", mss::c_str(i_target_mba),
+ l_port_index, l_dimm_index,
l_rank_index, l_nibble_index,
dram_num, best_pda_nibble_table[l_port_index][l_dimm_index][l_rank_index][l_nibble_index][0],
best_pda_nibble_table[l_port_index][l_dimm_index][l_rank_index][l_nibble_index][1]);
pda.push_back(PDA_MRS_Storage(0x01, fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE, dram_num, l_dimm_index, l_rank_index,
l_port_index));
- FAPI_INF("PDA STRING: %s %d %s", mss::c_str(i_target_mba), pda.size() - 1, pda[pda.size() - 1].c_str());
+ FAPI_INF("%s PDA STRING: %d %s", mss::c_str(i_target_mba), pda.size() - 1, pda[pda.size() - 1].c_str());
pda.push_back(PDA_MRS_Storage(max_vref, fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, dram_num, l_dimm_index, l_rank_index,
l_port_index));
- FAPI_INF("PDA STRING: %s %d %s", mss::c_str(i_target_mba), pda.size() - 1, pda[pda.size() - 1].c_str());
+ FAPI_INF("%s PDA STRING: %d %s", mss::c_str(i_target_mba), pda.size() - 1, pda[pda.size() - 1].c_str());
}
@@ -982,14 +1192,14 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
} //end of dimm loop
} //End of Port Loop
- FAPI_INF("RUNNING PDA FOR 1ST TIME");
+ FAPI_INF("%s RUNNING PDA FOR 1ST TIME", mss::c_str(i_target_mba));
FAPI_TRY(mss_ddr4_run_pda((fapi2::Target<fapi2::TARGET_TYPE_MBA>&)i_target_mba, pda));
- FAPI_INF("FINISHED RUNNING PDA FOR 1ST TIME");
+ FAPI_INF("%s FINISHED RUNNING PDA FOR 1ST TIME", mss::c_str(i_target_mba));
//issue call to run PDA again (latching good value in train mode)
- FAPI_INF("RUNNING PDA FOR 2ND TIME");
+ FAPI_INF("%s RUNNING PDA FOR 2ND TIME", mss::c_str(i_target_mba));
FAPI_TRY(mss_ddr4_run_pda((fapi2::Target<fapi2::TARGET_TYPE_MBA>&)i_target_mba, pda));
- FAPI_INF("FINISHED RUNNING PDA FOR 2ND TIME");
+ FAPI_INF("%s FINISHED RUNNING PDA FOR 2ND TIME", mss::c_str(i_target_mba));
//clear the PDA vector
pda.clear();
@@ -1031,15 +1241,15 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
} //end of dimm loop
} //End of Port Loop
- FAPI_INF("RUNNING PDA FOR 3RD TIME");
+ FAPI_INF("%s RUNNING PDA FOR 3RD TIME", mss::c_str(i_target_mba));
//issue call to PDA command
FAPI_TRY(mss_ddr4_run_pda((fapi2::Target<fapi2::TARGET_TYPE_MBA>&)i_target_mba, pda));
- FAPI_INF("FINISHED RUNNING PDA FOR 3RD TIME");
+ FAPI_INF("%s FINISHED RUNNING PDA FOR 3RD TIME", mss::c_str(i_target_mba));
} //End of Else
//turn on refresh then exit
FAPI_TRY(fapi2::getScom( i_target_mba, CEN_MBA_MBAREF0Q, refresh_reg));
- refresh_reg.setBit<0>();
+ refresh_reg.setBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom( i_target_mba, CEN_MBA_MBAREF0Q, refresh_reg));
} // end of if
@@ -1048,10 +1258,11 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
{
vref_val_print = base_percent + (vpd_wr_vref_value[0] * index_mul_print);
- FAPI_INF("The Vref value is from VPD = %d; The Voltage bump = %d ", vpd_wr_vref_value[0], vref_val_print);
+ FAPI_INF("%s The Vref value is from VPD = %d; The Voltage bump = %d ", mss::c_str(i_target_mba), vpd_wr_vref_value[0],
+ vref_val_print);
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.clearBit<0>();
+ l_data_buffer_64.clearBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
//FAPI_INF("\n After Clearing Refresh");
@@ -1104,7 +1315,7 @@ fapi2::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi2::Target<fapi2::TARGET_TYPE_
FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE, i_target_mba, vrefdq_train_enable));
FAPI_TRY(p9c_mss_mrs6_DDR4(i_target_mba), "mrs_load failed");
FAPI_TRY(fapi2::getScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
- l_data_buffer_64.setBit<0>();
+ l_data_buffer_64.setBit<REFRESH_BIT>();
FAPI_TRY(fapi2::putScom(i_target_mba, CEN_MBA_MBAREF0Q, l_data_buffer_64));
}
@@ -1132,7 +1343,7 @@ fapi2::ReturnCode rcv_imp_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_t
uint8_t l_rcv_imp_dq_dqs_nom[MAX_PORTS_PER_MBA] = {0};
uint8_t l_rcv_imp_dq_dqs_nom_fc = 0;
uint8_t l_rcv_imp_dq_dqs_in = 0;
- uint32_t l_rcv_imp_dq_dqs_schmoo[MAX_PORTS_PER_MBA] = {0};
+ uint32_t l_rcv_imp_dq_dqs_shmoo[MAX_PORTS_PER_MBA] = {0};
uint8_t index = 0;
uint8_t count = 0;
uint8_t shmoo_param_count = 0;
@@ -1144,20 +1355,20 @@ fapi2::ReturnCode rcv_imp_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_t
uint32_t l_right_margin_rcv_imp_array[MAX_RCV_IMP] = {0};
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS, i_target_mba, l_rcv_imp_dq_dqs_nom));
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_rcv_imp_dq_dqs_schmoo));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, i_target_mba, l_rcv_imp_dq_dqs_shmoo));
FAPI_INF("+++++++++++++++++RECIVER IMP Read Shmoo Attributes values+++++++++++++++");
FAPI_INF("CEN_RCV_IMP_DQ_DQS[0] = %d , CEN_RCV_IMP_DQ_DQS[1] = %d on %s",
l_rcv_imp_dq_dqs_nom[0],
l_rcv_imp_dq_dqs_nom[1],
mss::c_str(i_target_mba));
- FAPI_INF("CEN_RCV_IMP_DQ_DQS_SCHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SCHMOO[1] = [%d], on %s",
- l_rcv_imp_dq_dqs_schmoo[0],
- l_rcv_imp_dq_dqs_schmoo[1],
+ FAPI_INF("CEN_RCV_IMP_DQ_DQS_SHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SHMOO[1] = [%d], on %s",
+ l_rcv_imp_dq_dqs_shmoo[0],
+ l_rcv_imp_dq_dqs_shmoo[1],
mss::c_str(i_target_mba));
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
- if (l_rcv_imp_dq_dqs_schmoo[i_port] == 0)
+ if (l_rcv_imp_dq_dqs_shmoo[i_port] == 0)
{
FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings");
}
@@ -1165,7 +1376,7 @@ fapi2::ReturnCode rcv_imp_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_t
{
for (index = 0; index < MAX_RCV_IMP; index += 1)
{
- if ((l_rcv_imp_dq_dqs_schmoo[i_port] & MASK) == 1)
+ if ((l_rcv_imp_dq_dqs_shmoo[i_port] & MASK) == 1)
{
l_rcv_imp_dq_dqs[i_port] = rcv_imp_array[index];
FAPI_INF("Current Receiver Impedance: %d Ohms ",
@@ -1193,7 +1404,7 @@ fapi2::ReturnCode rcv_imp_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_t
l_right_margin_rcv_imp_array[index] = 0;
}
- l_rcv_imp_dq_dqs_schmoo[i_port] = (l_rcv_imp_dq_dqs_schmoo[i_port] >> 1);
+ l_rcv_imp_dq_dqs_shmoo[i_port] = (l_rcv_imp_dq_dqs_shmoo[i_port] >> 1);
}
l_rcv_imp_dq_dqs_nom_fc = l_rcv_imp_dq_dqs_nom[i_port];
@@ -1247,8 +1458,9 @@ fapi2::ReturnCode delay_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_tar
// then use an in-place new to put the object in the pre-allocated memory
void* l_mallocptr = malloc(sizeof(generic_shmoo));
generic_shmoo* l_pShmoo = new (l_mallocptr) generic_shmoo(i_port, i_shmoo_type_valid, SEQ_LIN);
- FAPI_TRY(l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin, i_shmoo_param), "Delay Schmoo Function is Failed");
+ FAPI_TRY(l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin, i_shmoo_param), "Delay Shmoo Function is Failed");
free(l_mallocptr);
+ FAPI_TRY(mcb_reset_error_flags(i_target_mba));
fapi_try_exit:
return fapi2::current_err;
@@ -1280,6 +1492,7 @@ fapi2::ReturnCode delay_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>&
FAPI_TRY(l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin, i_shmoo_param));
free(l_mallocptr);
+ FAPI_TRY(mcb_reset_error_flags(i_target_mba));
fapi_try_exit:
return fapi2::current_err;
@@ -1313,6 +1526,7 @@ fapi2::ReturnCode delay_shmoo_ddr4_pda(const fapi2::Target<fapi2::TARGET_TYPE_MB
FAPI_TRY(l_pShmoo->get_nibble_pda(i_target_mba, i_pda_nibble_table));
free(l_mallocptr);
+ FAPI_TRY(mcb_reset_error_flags(i_target_mba));
fapi_try_exit:
return fapi2::current_err;
@@ -1341,11 +1555,11 @@ fapi2::ReturnCode rd_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
shmoo_type_t l_shmoo_type_valid = MCBIST; // Hard coded - Temporary
fapi2::buffer<uint64_t> l_data_buffer_64;
fapi2::buffer<uint64_t> data_buffer;
- uint32_t l_rd_cen_vref_schmoo[MAX_PORTS_PER_MBA] = {0};
+ uint32_t l_rd_cen_vref_shmoo[MAX_PORTS_PER_MBA] = {0};
uint32_t l_left_margin = 0;
uint32_t l_right_margin = 0;
uint32_t l_rd_cen_vref_in = 0;
- uint8_t l_attr_schmoo_test_type_u8 = 1;
+ uint8_t l_attr_shmoo_test_type_u8 = 1;
uint8_t i_port = 0;
uint32_t diff_value = 1375;
uint32_t base = 70000;
@@ -1355,7 +1569,7 @@ fapi2::ReturnCode rd_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
uint8_t l_vref_num = 0;
uint8_t l_vref_num_tmp = 0;
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only - DDR4 +++++++++++++++++++++++++++");
FAPI_TRY(delay_shmoo(i_target_mba, i_port, l_shmoo_type_valid,
&l_left_margin, &l_right_margin,
@@ -1364,19 +1578,19 @@ fapi2::ReturnCode rd_vref_shmoo_ddr4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>
FAPI_TRY(set_attribute(i_target_mba));
l_shmoo_type_valid = RD_EYE;
- l_attr_schmoo_test_type_u8 = 4;
- FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_schmoo_test_type_u8));
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_RD_VREF_SCHMOO, i_target_mba, l_rd_cen_vref_schmoo));
+ l_attr_shmoo_test_type_u8 = 4;
+ FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_EFF_SCHMOO_TEST_VALID, i_target_mba, l_attr_shmoo_test_type_u8));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_CEN_RD_VREF_SCHMOO, i_target_mba, l_rd_cen_vref_shmoo));
- FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%x], CEN_RD_VREF_SCHMOO[1] = [%x] on %s",
- l_rd_cen_vref_schmoo[0],
- l_rd_cen_vref_schmoo[1],
+ FAPI_INF("CEN_RD_VREF_SHMOO[0] = [%x], CEN_RD_VREF_SHMOO[1] = [%x] on %s",
+ l_rd_cen_vref_shmoo[0],
+ l_rd_cen_vref_shmoo[1],
mss::c_str(i_target_mba));
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF DDR4 +++++++++++++++++++++++++++");
//For DDR3 - DDR4 Range
- if (l_rd_cen_vref_schmoo[i_port] == 1)
+ if (l_rd_cen_vref_shmoo[i_port] == 1)
{
FAPI_INF("\n Testing Range - DDR3 to DDR4 - Vrefs");
base = 50000;
@@ -1529,7 +1743,7 @@ fapi_try_exit:
/// @param[in] i_shmoo_param_valid PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
/// @param[in] i_left[] timing margin array
/// @param[in] i_right[] timing margin array
-/// @param[in] i_max Max enum value of schmoo param
+/// @param[in] i_max Max enum value of shmoo param
/// @param[in] i_param_nom selected shmoo parameter (DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP)
/// @param[in] o_index returns index
///
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.mk b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.mk
index 59c566711..7288e4029 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.mk
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.mk
@@ -5,7 +5,7 @@
#
# OpenPOWER HostBoot Project
#
-# Contributors Listed Below - COPYRIGHT 2016,2017
+# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
@@ -37,4 +37,6 @@ lib${PROCEDURE}_DEPLIBS+=p9c_mss_unmask_errors
lib${PROCEDURE}_DEPLIBS+=p9c_mss_mrs6_DDR4
lib${PROCEDURE}_DEPLIBS+=p9c_mss_access_delay_reg
lib${PROCEDURE}_DEPLIBS+=p9c_mss_funcs
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_ddr4_funcs
+lib${PROCEDURE}_DEPLIBS+=p9c_mss_ddr4_pda
$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C
index 1db9e4476..e22376c1f 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.C
@@ -27,7 +27,7 @@
/// @file p9c_mss_generic_shmoo.C
/// @brief MSS Generic Shmoo Implementation
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
@@ -241,8 +241,8 @@ extern "C"
FAPI_DBG("mss_generic_shmoo : run() l_attr_schmoo_test_type_u8 %d", l_attr_schmoo_test_type_u8);
// Check if all bytes/bits are in a pass condition initially .Otherwise quit
- //Value of l_attr_schmoo_test_type_u8 are 0x01, 0x02, 0x04, 0x08, 0x10 ===
- // "MCBIST","WR_EYE","RD_EYE","WRT_DQS","RD_DQS" resp.
+ //Value of l_attr_schmoo_test_type_u8 are 0x01, 0x02, 0x04, 0x08, 0x10 , 0x20 ===
+ // "MCBIST","WR_EYE","RD_EYE","WRT_DQS","RD_DQS","BOX" resp.
if (l_attr_schmoo_test_type_u8 == 0)
{
@@ -258,6 +258,19 @@ extern "C"
}
+ //runs the box shmoo
+ else if (l_attr_schmoo_test_type_u8 == BOX)
+ {
+ FAPI_TRY(get_all_noms(i_target));
+
+ if(l_attr_schmoo_multiple_setup_call_u8 == 0)
+ {
+ FAPI_TRY(schmoo_setup_mcb(i_target));
+ }
+
+ FAPI_TRY(do_box_shmoo(i_target));
+ }
+
else if (l_attr_schmoo_test_type_u8 == 8)
{
if (l_rankpgrp0[0] != 255)
@@ -4588,4 +4601,168 @@ extern "C"
return fapi2::current_err;
}
+ ///
+ /// @brief Box shmoo error log helper
+ /// @param[in] i_target the MBA target
+ /// @param[in] i_fail true if MCBIST failed
+ /// @param[in] i_vref the VREF value
+ /// @param[in] i_delay delay offset value
+ /// @param[in] i_offset true if the delay is positive
+ ///
+ fapi2::ReturnCode box_shmoo_error_helper(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target,
+ const bool i_fail,
+ const uint8_t i_vref,
+ const uint8_t i_delay,
+ const bool i_offset)
+ {
+ const bool l_pass = !i_fail;
+ FAPI_ASSERT(l_pass,
+ fapi2::MSS_BOX_SHMOO_FAIL()
+ .set_TARGET(i_target)
+ .set_VREF(i_vref)
+ .set_DELAY(i_delay)
+ .set_OFFSET(i_offset),
+ "%s FOUND FAILING MCBIST BIT AT %s 0x%02x DELAY and VREF 0x%02x!!!", mss::c_str(i_target), i_offset ? "+" : "-",
+ i_delay, i_vref)
+
+ // Passing - send out an informational message and return success
+ FAPI_INF("%s FOUND PASSING MCBIST BIT AT %s 0x%02x DELAY and VREF 0x%02x!!!", mss::c_str(i_target),
+ i_offset ? "+" : "-", i_delay, i_vref);
+ return fapi2::FAPI2_RC_SUCCESS;
+
+ fapi_try_exit:
+ // We're here, so we took a fail - log it as recovered, as we just want it to be informational
+ // Box shmoo is just used to collect data in case we take fails later
+ fapi2::logError(fapi2::current_err, fapi2::FAPI2_ERRL_SEV_RECOVERED);
+ fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Does the box shmoo
+ /// @param[in] i_target Centaur input MBA
+ /// @return FAPI2_RC_SUCCESS iff successful
+ ///
+ fapi2::ReturnCode generic_shmoo::do_box_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target)
+ {
+ fapi2::buffer<uint64_t> data_buffer_64;
+ uint8_t l_p = 0;
+ uint8_t l_rank = 0;
+ uint8_t l_dq = 0;
+ uint8_t l_n = 0;
+ uint8_t rank = 0;
+ uint8_t l_SCHMOO_NIBBLES = 18;
+ input_type_t l_input_type_e = WR_DQ;
+ access_type_t l_access_type_e = WRITE;
+
+ uint8_t delay_train_step_size = 0;
+ FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CEN_MRW_WR_VREF_CHECK_VREF_STEP_SIZE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ delay_train_step_size));
+
+ for(l_p = 0; l_p < MAX_PORT; l_p++)
+ {
+
+ for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++)
+ {
+ rank = valid_rank1[l_p][l_rank];
+
+ for(l_dq = 0; l_dq < BITS_PER_NIBBLE; l_dq++)
+ {
+ for (l_n = 0; l_n < l_SCHMOO_NIBBLES; l_n++)
+ {
+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq + l_n * BITS_PER_NIBBLE] =
+ (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq
+ + l_n * 4] + delay_train_step_size);
+ FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq + l_n * BITS_PER_NIBBLE,
+ 0,
+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq + l_n * BITS_PER_NIBBLE]));
+ }
+ }
+ }
+ }
+
+ FAPI_TRY(do_mcbist_reset(i_target), "%s generic_shmoo::find_bound do_mcbist_reset failed", mss::c_str(i_target));
+ FAPI_TRY(do_mcbist_test(i_target), "%s generic_shmoo::find_bound do_mcbist_test failed", mss::c_str(i_target));
+
+ FAPI_TRY(getScom(i_target, CEN_MBA_MCB_CNTLSTATQ, data_buffer_64));
+
+ // Note: the below function checks if we failed and logs an error if we did
+ // Box shmoo is a margins check, as such we want to just note the fail and move on in the IPL
+ // If we fail, that's ok we might have adequate margins to run, but we'll want to note it and move on
+ // True for increasing delay
+ FAPI_TRY(box_shmoo_error_helper(i_target, data_buffer_64.getBit<2>(), iv_vref_mul, delay_train_step_size, true));
+
+ {
+
+ uint8_t l_CDarray0[DIMM_TO_C4_DQ_ENTRIES] = { 0 };
+ uint8_t l_CDarray1[DIMM_TO_C4_DQ_ENTRIES] = { 0 };
+ FAPI_TRY(mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1,
+ count_bad_dq), "Failed mcb_error_map");
+ }
+
+ for(l_p = 0; l_p < MAX_PORT; l_p++)
+ {
+
+ for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++)
+ {
+ rank = valid_rank1[l_p][l_rank];
+
+ for(l_dq = 0; l_dq < BITS_PER_NIBBLE; l_dq++)
+ {
+ for (l_n = 0; l_n < l_SCHMOO_NIBBLES; l_n++)
+ {
+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq + l_n * BITS_PER_NIBBLE] =
+ (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq
+ + l_n * 4] - delay_train_step_size);
+
+ FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq + l_n * BITS_PER_NIBBLE,
+ 0,
+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq + l_n * BITS_PER_NIBBLE]));
+ }
+ }
+ }
+ }
+
+
+ FAPI_TRY(do_mcbist_reset(i_target), "%s generic_shmoo::find_bound do_mcbist_reset failed", mss::c_str(i_target));
+ FAPI_TRY(do_mcbist_test(i_target), "%s generic_shmoo::find_bound do_mcbist_test failed", mss::c_str(i_target));
+
+ FAPI_TRY(getScom(i_target, CEN_MBA_MCB_CNTLSTATQ, data_buffer_64));
+
+ // Note: the below function checks if we failed and logs an error if we did
+ // Box shmoo is a margins check, as such we want to just note the fail and move on in the IPL
+ // If we fail, that's ok we might have adequate margins to run, but we'll want to note it and move on
+ // False for decreasing delay
+ FAPI_TRY(box_shmoo_error_helper(i_target, data_buffer_64.getBit<2>(), iv_vref_mul, delay_train_step_size, false));
+
+ {
+
+ uint8_t l_CDarray0[DIMM_TO_C4_DQ_ENTRIES] = { 0 };
+ uint8_t l_CDarray1[DIMM_TO_C4_DQ_ENTRIES] = { 0 };
+ FAPI_TRY(mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1,
+ count_bad_dq), "Failed mcb_error_map");
+ }
+
+ for(l_p = 0; l_p < MAX_PORT; l_p++)
+ {
+ for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++)
+ {
+ rank = valid_rank1[l_p][l_rank];
+
+ for(l_dq = 0; l_dq < BITS_PER_NIBBLE; l_dq++)
+ {
+ for (l_n = 0; l_n < l_SCHMOO_NIBBLES; l_n++)
+ {
+ FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq + l_n * BITS_PER_NIBBLE,
+ 0,
+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq + l_n * BITS_PER_NIBBLE]));
+ }
+ }
+ }
+ }
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
}//Extern C
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H
index 5a40fa7c8..4f282f991 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,7 +27,7 @@
/// @file mss_generic_shmoo.H
/// @brief Memory Subsystem Generic Shmoo -- abstraction for HB
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
@@ -142,6 +142,13 @@ class generic_shmoo
const bound_t);
///
+ /// @brief Does the box shmoo
+ /// @param[in] i_target Centaur input MBA
+ /// @return FAPI2_RC_SUCCESS iff successful
+ ///
+ fapi2::ReturnCode do_box_shmoo(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target);
+
+ ///
/// @brief This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag
/// @param[in] i_target Centaur input MBA Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass,
/// @param[in] bound RIGHT/LEFT
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H
index 7b2d9de09..7b54fc0e1 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H
@@ -27,7 +27,7 @@
/// @file mss_mcbist.H
/// @brief MCBIST execution procedures header
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Steve Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
@@ -50,59 +50,59 @@ extern "C"
///
enum mcbist_test_mem
{
- USER_MODE,
- CENSHMOO,
- SUREFAIL,
- MEMWRITE,
- MEMREAD,
- CBR_REFRESH,
- MCBIST_SHORT,
- SHORT_SEQ,
- DELTA_I,
- DELTA_I_LOOP,
- SHORT_RAND,
- LONG1,
- BUS_TAT,
- SIMPLE_FIX,
- SIMPLE_RAND,
- SIMPLE_RAND_2W,
- SIMPLE_RAND_FIXD,
- SIMPLE_RA_RD_WR,
- SIMPLE_RA_RD_R,
- SIMPLE_RA_FD_R,
- SIMPLE_RA_FD_R_INF,
- SIMPLE_SA_FD_R,
- SIMPLE_RA_FD_W,
- INFINITE,
- WR_ONLY,
- W_ONLY,
- R_ONLY,
- W_ONLY_RAND,
- R_ONLY_RAND,
- R_ONLY_MULTI,
- SHORT,
- SIMPLE_RAND_BARI,
- W_R_INFINITE,
- W_R_RAND_INFINITE,
- R_INFINITE1,
- R_INFINITE_RF,
- MARCH,
- SIMPLE_FIX_RF,
- SHMOO_STRESS,
- SIMPLE_RAND_RA,
- SIMPLE_FIX_RA,
- SIMPLE_FIX_RF_RA,
- TEST_RR,
- TEST_RF,
- W_ONLY_INFINITE_RAND,
- MCB_2D_CUP_SEQ,
- MCB_2D_CUP_RAND,
- SHMOO_STRESS_INFINITE,
- HYNIX_1_COL,
- RMWFIX,
- RMWFIX_I,
- W_INFINITE,
- R_INFINITE
+ USER_MODE = 0,
+ CENSHMOO = 1,
+ SUREFAIL = 2,
+ MEMWRITE = 3,
+ MEMREAD = 4,
+ CBR_REFRESH = 5,
+ MCBIST_SHORT = 6,
+ SHORT_SEQ = 7,
+ DELTA_I = 8,
+ DELTA_I_LOOP = 9,
+ SHORT_RAND = 10,
+ LONG1 = 11,
+ BUS_TAT = 12,
+ SIMPLE_FIX = 13,
+ SIMPLE_RAND = 14,
+ SIMPLE_RAND_2W = 15,
+ SIMPLE_RAND_FIXD = 16,
+ SIMPLE_RA_RD_WR = 17,
+ SIMPLE_RA_RD_R = 18,
+ SIMPLE_RA_FD_R = 19,
+ SIMPLE_RA_FD_R_INF = 20,
+ SIMPLE_SA_FD_R = 21,
+ SIMPLE_RA_FD_W = 22,
+ INFINITE = 23,
+ WR_ONLY = 24,
+ W_ONLY = 25,
+ R_ONLY = 26,
+ W_ONLY_RAND = 27,
+ R_ONLY_RAND = 28,
+ R_ONLY_MULTI = 29,
+ SHORT = 30,
+ SIMPLE_RAND_BARI = 31,
+ W_R_INFINITE = 32,
+ W_R_RAND_INFINITE = 33,
+ R_INFINITE1 = 34,
+ R_INFINITE_RF = 35,
+ MARCH = 36,
+ SIMPLE_FIX_RF = 37,
+ SHMOO_STRESS = 38,
+ SIMPLE_RAND_RA = 39,
+ SIMPLE_FIX_RA = 40,
+ SIMPLE_FIX_RF_RA = 41,
+ TEST_RR = 42,
+ TEST_RF = 43,
+ W_ONLY_INFINITE_RAND = 44,
+ MCB_2D_CUP_SEQ = 45,
+ MCB_2D_CUP_RAND = 46,
+ SHMOO_STRESS_INFINITE = 47,
+ HYNIX_1_COL = 48,
+ RMWFIX = 49,
+ RMWFIX_I = 50,
+ W_INFINITE = 51,
+ R_INFINITE = 52,
};
// This is the number of tests in the enum above
constexpr uint64_t MAX_MCBIST_TEST_INDEX = 52;
@@ -443,5 +443,12 @@ extern "C"
void mss_conversion_data(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba,
const uint8_t l_pattern,
mcbist_data_gen& o_mcbpatt);
+
+ ///
+ /// @brief Resets the error flag registers
+ /// @param[in] i_target_mba Centaur input MBA
+ /// @return FAPI2_RC_SUCCESS iff successful
+ ///
+ fapi2::ReturnCode mcb_reset_error_flags(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba);
}
#endif
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_address.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_address.C
index 79fb0dc86..82f6255e3 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_address.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_address.C
@@ -27,7 +27,7 @@
/// @file mss_mcbist_address.C
/// @brief MCBIST address generation procedures
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Steve Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
@@ -53,6 +53,7 @@ extern "C"
{
uint8_t l_num_ranks_per_dimm[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
uint8_t l_num_master_ranks[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0};
+ uint8_t l_dimm_eff_ibm_type[2][2] = {0};
uint8_t l_dram_rows = 0;
uint8_t l_dram_cols = 0;
uint8_t l_addr_inter = 0;
@@ -70,6 +71,7 @@ extern "C"
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_ROWS, i_target_mba, l_dram_rows));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_COLS, i_target_mba, l_dram_cols));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_ADDR_INTER, i_target_mba, l_addr_inter));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_IBM_TYPE, i_target_mba, l_dimm_eff_ibm_type));
l_num_ranks_p0_dim0 = l_num_ranks_per_dimm[0][0];
l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1];
@@ -86,6 +88,7 @@ extern "C"
sl2_valid = 0;
sl1_valid = 0;
sl0_valid = 0;
+ FAPI_INF("%s Calling address generation!\n", mss::c_str(i_target_mba));
if( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 1
&& l_num_ranks_p1_dim1 == 0) ) //Single Rank case -- default0
@@ -115,17 +118,37 @@ extern "C"
mr3_valid = 1;
mr1_valid = 1;
}
+ else if ((l_num_ranks_p0_dim0 == 4 || l_num_ranks_p0_dim1 == 4 || l_num_ranks_p1_dim0 == 4 || l_num_ranks_p1_dim1 == 4)
+ && (l_dimm_eff_ibm_type[0][0] == 8)) //Type 3A - 4R 2M2S, 2H 3DS TSV Stack, ISDIMM
+ {
+ FAPI_INF("%s - IBM Type 3A - 2M2S ISDIMM", mss::c_str(i_target_mba));
+ sl0_valid = 0;
+ sl1_valid = 0;
+ sl2_valid = 1;
+ mr3_valid = 1;
+ }
+ else if ((l_num_ranks_p0_dim0 == 8 || l_num_ranks_p0_dim1 == 8 || l_num_ranks_p1_dim0 == 8 || l_num_ranks_p1_dim1 == 8)
+ && (l_dimm_eff_ibm_type[0][0] == 9)) //Type 3B - 8R 2M4S, 4H 3DS TSV Stack, ISDIMM
+ {
+ FAPI_INF("%s - IBM Type 3B - 2M4S ISDIMM", mss::c_str(i_target_mba));
+ sl0_valid = 0;
+ sl1_valid = 1;
+ sl2_valid = 1;
+ mr3_valid = 1;
+ }
else if((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 0 ) || (l_num_ranks_p1_dim0 == 4
&& l_num_ranks_p1_dim1 == 0 )) //Rank 0123 on single dimm case
{
+ FAPI_DBG("%s:--- INSIDE --- 4R0R 0123", mss::c_str(i_target_mba));
mr3_valid = 1;
mr2_valid = 1;
}
else if (((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4
&& l_num_ranks_p1_dim1 == 4)) && l_master_ranks_p0_dim0 == 1) //1r 4h stack
{
- mr1_valid = 0; //DDC
+ FAPI_DBG("%s:--- INSIDE --- 4R4R - 4H", mss::c_str(i_target_mba));
+ mr1_valid = 1; //DDC
sl1_valid = 1;
sl2_valid = 1;
}
@@ -134,6 +157,7 @@ extern "C"
&& l_num_ranks_p1_dim1 == 0)) && ((l_master_ranks_p0_dim0 == 2) || (l_master_ranks_p0_dim1 == 0
&& l_master_ranks_p1_dim0 == 2))) //2rx4 4h ddr4 3ds
{
+ FAPI_DBG("%s:--- INSIDE --- 8R0R - 8H 0123", mss::c_str(i_target_mba));
l_addr_inter = 4;
mr3_valid = 1; //DDC
sl1_valid = 1;
@@ -142,6 +166,7 @@ extern "C"
else if ((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4
&& l_num_ranks_p1_dim1 == 4)) //Rank 0123 and 4567 case
{
+ FAPI_DBG("%s:--- INSIDE --- 4R4R - 01234567", mss::c_str(i_target_mba));
mr3_valid = 1;
mr2_valid = 1;
mr1_valid = 1;
@@ -150,6 +175,7 @@ extern "C"
(l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) &&
(l_master_ranks_p0_dim0 == 1 && l_master_ranks_p0_dim1 == 1)) //1rx4 2h ddr4 3ds 2 dimm, CDIMM
{
+ FAPI_DBG("%s:--- INSIDE --- 2R2R - 2H 04", mss::c_str(i_target_mba));
sl1_valid = 0;
sl2_valid = 1;
mr1_valid = 1;
@@ -221,6 +247,16 @@ extern "C"
uint8_t l_num_rows = 0;
uint8_t l_dram_gen = 0;
+ FAPI_INF("Running parse address %u %u %u %u %u %u %u %u %u!", mr3_valid,
+ mr2_valid,
+ mr1_valid,
+ l_dram_rows,
+ l_dram_cols,
+ l_addr_inter,
+ sl2_valid,
+ sl1_valid,
+ sl0_valid);
+
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_SCHMOO_ADDR_MODE, i_target_mba, l_attr_addr_mode));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_ADDR_NUM_COLS, i_target_mba, l_num_cols));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MCBIST_ADDR_NUM_ROWS, i_target_mba, l_num_rows));
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C
index d660d280a..e55a8a4a1 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C
@@ -27,7 +27,7 @@
/// @file mss_mcbist_common.C
/// @brief mcbist procedures
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
/// *HWP HWP Backup: Steve Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
@@ -220,12 +220,66 @@ extern "C"
}
///
+ /// @brief Resets the error flag registers
+ /// @param[in] i_target_mba Centaur input MBA
+ /// @return FAPI2_RC_SUCCESS iff successful
+ ///
+ fapi2::ReturnCode mcb_reset_error_flags(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba)
+ {
+ static const std::vector<uint32_t> MBA01_ERROR_TRAP =
+ {
+ CEN_MCBISTS01_MCBEMA1Q,
+ CEN_MCBISTS01_MCBEMA2Q,
+ CEN_MCBISTS01_MCBEMA3Q,
+ CEN_MCBISTS01_MCBEMB1Q,
+ CEN_MCBISTS01_MCBEMB2Q,
+ CEN_MCBISTS01_MCBEMB3Q,
+ };
+ static const std::vector<uint32_t> MBA23_ERROR_TRAP =
+ {
+ CEN_MCBISTS23_MCBEMA1Q,
+ CEN_MCBISTS23_MCBEMA2Q,
+ CEN_MCBISTS23_MCBEMA3Q,
+ CEN_MCBISTS23_MCBEMB1Q,
+ CEN_MCBISTS23_MCBEMB2Q,
+ CEN_MCBISTS23_MCBEMB3Q,
+ };
+
+ uint8_t l_mba_position = 0;
+ const auto i_target_centaur = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_mba, l_mba_position));
+
+ {
+ FAPI_INF("%s resetting the MCBIST error flags", mss::c_str(i_target_mba));
+
+ // So, the crappy thing about centaur is that not all registers tied to an MBA are on the MBA chiplet
+ // Certain registers are on an MBS chiplet. MBS chiplet 0 is tied to MBA chiplet 0, while
+ // MBS chiplet 1 is tied to MBA chiplet 1. However, as the scoms are on different chiplets,
+ // and the hardware implementation does not support an MBS chiplet, we need to figure out which scoms registers
+ // to hit. We're assigning them below
+ const auto& l_trap_vector = l_mba_position == 0 ? MBA01_ERROR_TRAP : MBA23_ERROR_TRAP;
+
+ // Now, loop through and reset all of the error traps
+ for(const auto l_reg : l_trap_vector)
+ {
+ fapi2::buffer<uint64_t> l_data_buffer_64;
+ FAPI_TRY(fapi2::putScom(i_target_centaur, l_reg, l_data_buffer_64));
+ }
+ }
+
+ fapi_try_exit:
+ return fapi2::current_err;
+
+ }
+
+ ///
/// @brief Clears all the trap registers in MCBIST engine
/// @param[in] i_target_mba Centaur input mba
/// @return FAPI2_RC_SUCCESS iff successful
///
fapi2::ReturnCode mcb_reset_trap(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target_mba)
{
+
fapi2::buffer<uint64_t> l_data_buffer_64;
uint8_t l_mba_position = 0;
const auto i_target_centaur = i_target_mba.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
@@ -248,6 +302,10 @@ extern "C"
FAPI_TRY(fapi2::putScom(i_target_centaur, CEN_MCBISTS23_MCBCMA1Q, l_data_buffer_64));
FAPI_TRY(fapi2::putScom(i_target_centaur, CEN_MCBISTS23_MCBCMB1Q, l_data_buffer_64));
FAPI_TRY(fapi2::putScom(i_target_centaur, CEN_MCBISTS23_MCBCMABQ, l_data_buffer_64));
+
+ // Resets the error flags
+ FAPI_TRY(mcb_reset_error_flags(i_target_mba));
+
fapi_try_exit:
return fapi2::current_err;
}
@@ -2503,7 +2561,8 @@ extern "C"
break;
default:
- FAPI_INF("%s:Wrong Data Pattern,so using default pattern",
+ o_mcbpatt = ABLE_FIVE;
+ FAPI_INF("%s:Wrong Data Pattern,so using default pattern of ABLE_FIVE",
mss::c_str(i_target_mba));
}
}
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_shmoo_common.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_shmoo_common.H
index 0cf8393a0..fc3200417 100755
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_shmoo_common.H
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_shmoo_common.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -27,8 +27,8 @@
/// @file mss_shmoo_common.H
/// @brief Tools for DDR4 DIMMs centaur procedures
///
-/// *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com>
-/// *HWP HWP Backup: steve glancy <sglancy@us.ibm.com>
+/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
+/// *HWP HWP Backup: Steve Glancy <sglancy@us.ibm.com>
/// *HWP Team: Memory
/// *HWP Level: 2
/// *HWP Consumed by: HB:CI
@@ -43,13 +43,13 @@
///
/// @brief shmoo type enums
///
-enum shmoo_type_t
+enum shmoo_type_t : uint8_t
{
TEST_NONE = 0,
MCBIST = 1,
WR_EYE = 2,
- WRT_DQS = 8,
RD_EYE = 4,
+ WRT_DQS = 8,
RD_GATE = 16,
BOX = 32
};
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
index 248fda9ef..77b49ddaa 100644
--- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml
@@ -121,11 +121,12 @@ Set by: PLL settings written by Dave Cadigan</description>
<attribute>
<id>ATTR_CEN_MSS_VREF_CAL_CNTL</id>
<targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
- <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level;
- Default Value = 0x03 for OpenPower platforms
- = 0x01 for others (TULETA, BRAZOS, ALPINE).
+ <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=Box shmoo;
+ Default Value = 0x03 for box shmoo on all platforms
</description>
<valueType>uint8</valueType>
+ <enum>DISABLE = 0, DRAM = 1, RANK = 2, BOX = 3</enum>
+ <default>3</default>
<platInit/>
<odmVisable/>
<odmChangeable/>
@@ -1636,7 +1637,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_MODE</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
+ <description>Specifies the shmoo mode to use during draminit_train_adv.</description>
<valueType>uint8</valueType>
<enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum>
<writeable/>
@@ -1647,7 +1648,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_ADDR_MODE</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo mode to use during draminit_train_adv</description>
+ <description>Specifies the shmoo mode to use during draminit_train_adv</description>
<valueType>uint8</valueType>
<enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
<writeable/>
@@ -1658,14 +1659,15 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_TEST_VALID</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
+ <description>Specifies the shmoo test to run during draminit_train_adv. Bit wise.</description>
<valueType>uint8</valueType>
<enum> NONE = 0x00,
MCBIST = 0x01,
WR_EYE = 0x02,
RD_EYE = 0x04,
WR_DQS = 0x08,
- RD_DQS = 0x10</enum>
+ RD_DQS = 0x10,
+ BOX = 0x20</enum>
<writeable/>
<odmVisable/>
<odmChangeable/>
@@ -1674,7 +1676,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_PARAM_VALID</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description>
+ <description>Specifies the shmoo parameters to use during draminit_train_adv. Bit wise.</description>
<valueType>uint8</valueType>
<enum> PARAM_NONE = 0x00,
DELAY_REG = 0x01,
@@ -1691,7 +1693,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+ <description>Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
<valueType>uint8</valueType>
<writeable/>
<odmVisable/>
@@ -1701,7 +1703,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+ <description>Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
<valueType>uint8</valueType>
<writeable/>
<odmVisable/>
@@ -1711,7 +1713,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+ <description>Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
<valueType>uint8</valueType>
<writeable/>
<odmVisable/>
@@ -1721,7 +1723,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+ <description>Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
<valueType>uint8</valueType>
<writeable/>
<odmVisable/>
@@ -1731,7 +1733,7 @@ firmware notes: none</description>
<attribute>
<id>ATTR_CEN_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
<targetType>TARGET_TYPE_MBA</targetType>
- <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+ <description>Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
<valueType>uint8</valueType>
<writeable/>
<odmVisable/>
diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml
index b92b9cb18..61ebbb840 100644
--- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml
+++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_errors.xml
@@ -26,8 +26,8 @@
<!-- @file p9c_memory_errors.xml -->
<!-- @brief Error xml for memory errors-->
<!-- -->
-<!-- *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> -->
-<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -->
+<!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -->
+<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -->
<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> -->
<!-- *HWP Team: Memory -->
<!-- *HWP Level: 1 -->
@@ -361,6 +361,23 @@
</deconfigure>
</hwpError>
+<hwpError>
+ <rc>RC_MSS_BOX_SHMOO_FAIL</rc>
+ <description>Box shmoo failed at one corner</description>
+ <ffdc>TARGET</ffdc>
+ <ffdc>VREF</ffdc>
+ <ffdc>DELAY</ffdc>
+ <ffdc>OFFSET</ffdc>
+ <callout>
+ <target>TARGET</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
+</hwpError>
+
<!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID -->
</hwpErrors>
diff --git a/src/usr/isteps/istep13/call_mss_draminit_trainadv.C b/src/usr/isteps/istep13/call_mss_draminit_trainadv.C
index e281c5b80..6ba7c4bf3 100644
--- a/src/usr/isteps/istep13/call_mss_draminit_trainadv.C
+++ b/src/usr/isteps/istep13/call_mss_draminit_trainadv.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2017 */
+/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -118,6 +118,7 @@ void* call_mss_draminit_trainadv (void *io_pArgs)
// Make a local copy of the target for ease of use
TARGETING::Target* l_mbaTarget = *l_mba_iter;
+#if 0 //TODO CQ:SW430659 re-enable when VPD supports
// Dump current run on target
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"Running p9c_mss_draminit_training_advanced HWP on "
@@ -127,7 +128,11 @@ void* call_mss_draminit_trainadv (void *io_pArgs)
fapi2::Target <fapi2::TARGET_TYPE_MBA_CHIPLET> l_fapi_mba_target(l_mbaTarget);
FAPI_INVOKE_HWP(l_err, p9c_mss_draminit_training_advanced, l_fapi_mba_target);
-
+#else
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SKIPPING p9c_mss_draminit_training_advanced HWP on "
+ "target HUID %.8X till VPD ready", TARGETING::get_huid(l_mbaTarget));
+#endif
// process return code.
if ( l_err )
{
OpenPOWER on IntegriCloud