diff options
author | Stephen Glancy <sglancy@us.ibm.com> | 2018-04-02 15:29:43 -0500 |
---|---|---|
committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-04-20 10:47:56 -0400 |
commit | 38b16d88416d1e0fe8d352da4f5d8739e8bcbb33 (patch) | |
tree | 9a977f94616e3703e5c8f80d4263a70e754d6ca7 | |
parent | b6271f37908f731fd1721e4457d187b2124e9317 (diff) | |
download | talos-hostboot-38b16d88416d1e0fe8d352da4f5d8739e8bcbb33.tar.gz talos-hostboot-38b16d88416d1e0fe8d352da4f5d8739e8bcbb33.zip |
Adds centaur dynamic VDDR code
Change-Id: Ie6f0471da550f386b3558b274affad02d4f1b673
cmvc-coreq: 1052555
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56593
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56667
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
10 files changed, 637 insertions, 118 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C index 0fa861563..38aed25e9 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C +++ b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C @@ -22,3 +22,131 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// @file mss_dynamic_vid_utils.C +/// @brief Utility procedures for dyanamic voltage +/// +/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 3 +/// *HWP Consumed by: HB + +#include <mss_dynamic_vid_utils.H> +#include <generic/memory/lib/utils/find.H> + + + +/// +/// @brief Checks centaur configurations and outputs DRAM device type +/// @param[in] std::vector<fapi2::Target> l_targets Reference to vector of Centaur Targets in a particular power domain +/// @param[out] o_dram_type the DRAM device type (DDR3 or DDR4) +/// @return ReturnCode success IFF everything passes +/// @note Checks the following configuration items: +/// The DRAM generations are all the same +/// At least one functional centaur was found +/// +fapi2::ReturnCode check_dram_gen_plug(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>>& i_targets, + uint8_t& o_dram_gen) +{ + fapi2::ReturnCode l_bad_vpd_rc = fapi2::FAPI2_RC_SUCCESS; + bool l_has_functional_centaur = false; + bool l_dram_gen_found = false; + uint8_t l_cur_dram_gen = 0; + + // Checks to make sure that all of the DRAM generation attributes are the same, if not error out + // The reason behind this is that DDR3 and DDR4 require mutually exclusive voltage ranges + // For custom DIMM's someone could have violated plug rules and put a DDR3 and DDR4 DIMM on the same voltage rail + // In that case, we want to call out all of the DIMM that are improperly plugged and exit + for(const auto& l_chip : i_targets) + { + // Gets the functional attribute to check for an active centaur + uint8_t l_is_functional = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUNCTIONAL, l_chip, l_is_functional)); + + // Found a functional centaur, we won't error out now + if(l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + { + l_has_functional_centaur = true; + } + + for(const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(l_chip)) + { + // Gets the attributes and computes var_power_on based upon whether the DRAM type is DDR3 or DDR4 + auto l_rc = FAPI_ATTR_GET(fapi2::ATTR_CEN_SPD_DRAM_DEVICE_TYPE, l_dimm, l_cur_dram_gen); + + // Found an error reading the SPD/VPD, let's see if we can determine why + // Note: in centaur, if we're using ISDIMM's, then it's SPD + // If we're using CDIMM, then it's VPD + if(l_rc) + { + // If the dimm is functional, then we shouldn't have failed the access to the DRAM device type, log this DIMM as failing and proceed to the next one + // In order to reduce the size of the de-config loop, we want to callout ALL bad SPD/VPD + // At this point, we're assuming that the VPD read error is the fault of hardware + if(l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + { + const auto& l_mba = mss::find_target<fapi2::TARGET_TYPE_MBA>(l_dimm); + FAPI_ASSERT_NOEXIT(false, fapi2::CEN_MSS_VDDR_FUNCTIONAL_DIMM_VPD_READ_ERROR() + .set_DIMM_TARGET(l_dimm) + .set_MBA_TARGET(l_mba), + "Problem reading VPD on functional DIMM. Logging error and proceding to the next DIMM."); + + // Using a generic error here as we already logged the other error above + l_bad_vpd_rc = fapi2::FAPI2_RC_INVALID_PARAMETER; + } + // The DIMM is not functional, assume that bad VPD caused the attribute access fail + // Note the problem with an informational statement and skip this DIMM + else + { + FAPI_INF("Problem reading VPD on non-functional DIMM. Skipping current DIMM and proceding to the next DIMM."); + } + + continue; + } + + // If this is the first DIMM that has a valid DRAM Technology level, then set the level and continue + if(!l_dram_gen_found) + { + o_dram_gen = l_cur_dram_gen; + l_dram_gen_found = true; + } //end if + // Check if the DRAM levels are the same, if not, log the information and continue on + // Again, we want to callout as many badly configured DIMM as possible + else + { + // Values are not equal continue to call out all non-equal DRAM generations + if(l_cur_dram_gen != o_dram_gen) + { + const auto& l_mba = mss::find_target<fapi2::TARGET_TYPE_MBA>(l_dimm); + FAPI_ASSERT_NOEXIT(false, fapi2::CEN_MSS_VOLT_VDDR_OFFSET_DRAM_GEN_MISCOMPARE() + .set_DIMM_TARGET(l_dimm) + .set_MBA_TARGET(l_mba) + .set_DRAM_GEN_MISCOMPARE(l_cur_dram_gen) + .set_DRAM_GEN_START(o_dram_gen), + "Not all DRAM technology generations are the same. Exiting...."); + + // Using a generic error here as we already logged the other error above + l_bad_vpd_rc = fapi2::FAPI2_RC_INVALID_PARAMETER; + }//end if + + }//end else + } // end for DIMM + } // End for chip target + + // Found a bad VPD + FAPI_TRY(l_bad_vpd_rc, "DIMM configuration or hardware error. Check error logs"); + + // Did not find any functional centaurs + FAPI_ASSERT(l_has_functional_centaur, + fapi2::CEN_MSS_VOLT_VDDR_FUNCTIONAL_CENTAUR_NOT_FOUND() + .set_CEN_TARGET(i_targets[0]), + "%s No functional centaurs found! Exiting....", mss::c_str(i_targets[0])); + + // Checks to make sure that the code actually found a dimm with a value for its dram generation. if not, exit out + FAPI_ASSERT(l_dram_gen_found, + fapi2::CEN_MSS_VOLT_VDDR_DRAM_GEN_NOT_FOUND() + .set_CEN_TARGET(i_targets[0]), + "%s No DRAM generation found! Exiting....", mss::c_str(i_targets[0])); + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.H b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.H index e65ecaa09..3407fd215 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.H +++ b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.H @@ -22,3 +22,28 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// @file mss_dynamic_vid_utils.H +/// @brief Utility procedures for dyanamic voltage +/// +/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 3 +/// *HWP Consumed by: HB + +#ifndef MSS_DYNAMIC_VID_UTILS_H +#define MSS_DYNAMIC_VID_UTILS_H + +#include <fapi2.H> + +/// +/// @brief Checks centaur configurations and outputs DRAM device type +/// @param[in] std::vector<fapi2::Target> l_targets Reference to vector of Centaur Targets in a particular power domain +/// @param[out] o_dram_type the DRAM device type (DDR3 or DDR4) +/// @return ReturnCode success IFF everything passes +/// +fapi2::ReturnCode check_dram_gen_plug(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>>& i_targets, + uint8_t& o_dram_gen); + + +#endif // MSS_DYNAMIC_VID_UTILS_H diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C index 4be0b8f18..2cd518ef0 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C @@ -22,3 +22,314 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// @file p9c_mss_mss_volt_vddr_offset.C +/// @brief Creates VDDR voltage offsets +/// +/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 3 +/// *HWP Consumed by: HB + +// This procedure takes a vector of Centaurs behind the vddr voltage domain, +// reads in supported DIMM voltages from SPD and determines optimal +// voltage bin for the DIMM voltage domain. +// supported voltage bins: DDR3 1.35V DDR4 1.20V + + +//---------------------------------------------------------------------- +// Includes - FAPI +//---------------------------------------------------------------------- +#include <fapi2.H> +#include <p9c_mss_volt_vddr_offset.H> +#include <mss_dynamic_vid_utils.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/count_dimm.H> + +extern "C" +{ +/// +/// @brief mss_volt_vddr_offset procedure. Determines operating vddr voltage for dimms behind a vddr voltage domain +/// @param[in] i_targets Reference to vector of Centaur Targets in a particular vddr power domain +/// @return ReturnCode +/// + fapi2::ReturnCode p9c_mss_volt_vddr_offset(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>>& i_targets) + { + // If we're passed an empty vector, exit out + if(i_targets.empty()) + { + FAPI_INF("Empty vector of targets passed to VDDR offset. Exiting.."); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Constexpr's to pretty up some of the code + constexpr double PERCENT = 100; + constexpr uint64_t ATTR_VOLT_CONVERSION = 10000; + // Note: per the power/thermal team, 5625 is the utilization for the max DMI speed at 1600 memory frequency + // Please note, if dynamic VID is needed on all P9 centaur systems, then this value will become an MRW attribute + // Currently, dynamic voltage is only needed on custom DIMM systems, if it is needed on ISDIMM systems, then the data bus utilization code will need to change: + // ISDIMM systems could hypothetically have DIMM's on only one given MBA. In that case the data bus utilization will increase. We should then just look into using the attribute. + constexpr uint64_t DATA_BUS_UTIL = 5625; + + // Declares variables + fapi2::ReturnCode l_bad_vpd_rc = fapi2::FAPI2_RC_SUCCESS; + uint32_t l_vpd_master_power_slope = 0; + uint32_t l_vpd_master_power_intercept = 0; + uint32_t l_volt_util_active = 0; + uint32_t l_volt_util_inactive = 0; + uint32_t l_volt_slope = 0; + uint32_t l_volt_intercept = 0; + uint32_t l_good_master_power_slope = 0; + uint32_t l_good_master_power_intercept = 0; + uint32_t l_num_dimms_to_add = 0; + uint32_t l_var_power_on_vddr = 0; + uint32_t l_num_logical_dimms = 0; + uint8_t l_dram_gen = 0; + uint8_t l_enable = 0; + uint8_t l_is_functional = 0; + uint8_t l_ec_disable_attr = 0; + uint8_t l_percent_uplift = 0; + uint8_t l_percent_uplift_idle = 0; + uint32_t l_vddr_max_limit_mv = 0; + uint32_t l_param_vddr_voltage_mv = 0; + uint32_t l_data_bus_util = 0; + + // Gets and checks the DRAM generation and centaur configuration + // Note: Plug rules checks haven't been done up to this point + // The below checks that all DRAM have the same generation on this VDDR rail and returns the valid DRAM generation + FAPI_TRY(check_dram_gen_plug(i_targets, l_dram_gen)); + + // Voltage should not be updated if the disable is set + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDDR_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_enable)); + + // Attribute is disabled, just exit + if(l_enable == fapi2::ENUM_ATTR_MSS_MRW_VDDR_OFFSET_ENABLE_DISABLE) + { + FAPI_INF("ATTR_MSS_MRW_VDDR_OFFSET_ENABLE is set to be disabled. Exiting....., %d", l_enable); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Checks if any MC's have the disable attribute set, if so, set to MSS_VOLT value + // If not, continue with the code + for(const auto& l_chip : i_targets) + { + //reads in the attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_CENTAUR_EC_FEATURE_DISABLE_VDDR_DYNAMIC_VID, l_chip, l_ec_disable_attr)); + + // Disable is set, read mss_volt and exit out of the code + if(l_ec_disable_attr) + { + break; + } + } + + // Disable is set, sets the l_enable attribute based upon MSS_VOLT attribute + if(l_ec_disable_attr) + { + FAPI_INF("Found Centaur with EC disable attribute set. Setting ATTR_CEN_MSS_VDDR_OFFSET based upon ATTR_CEN_MSS_VOLT"); + + //sets the output attributes + for(const auto& l_chip : i_targets) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_VOLT, l_chip, l_param_vddr_voltage_mv)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MSS_VDDR_OFFSET, l_chip, l_param_vddr_voltage_mv)); + }//end for + + return fapi2::FAPI2_RC_SUCCESS; + } + + // Gets the attributes and computes var_power_on based upon whether the DRAM type is DDR3 or DDR4 + if(l_dram_gen == fapi2::ENUM_ATTR_CEN_SPD_DRAM_DEVICE_TYPE_DDR3) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_DDR3_VDDR_SLOPE, i_targets[0], l_volt_slope)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_DDR3_VDDR_INTERCEPT, i_targets[0], l_volt_intercept)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_DDR3_VDDR_MAX_LIMIT, i_targets[0], l_vddr_max_limit_mv)); + } + // DDR4 + else + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_DDR4_VDDR_SLOPE, i_targets[0], l_volt_slope)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MSS_DDR4_VDDR_INTERCEPT, i_targets[0], l_volt_intercept)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_MRW_DDR4_VDDR_MAX_LIMIT, i_targets[0], l_vddr_max_limit_mv)); + } + + // Gets the data bus utilization and picks the lower of the two values + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_data_bus_util)); + l_data_bus_util = l_data_bus_util < DATA_BUS_UTIL ? l_data_bus_util : DATA_BUS_UTIL; + + // Computes the active and inactive attribute values + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_percent_uplift)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_percent_uplift_idle)); + + + l_volt_util_active = l_data_bus_util; + l_volt_util_inactive = 0; + + // Checks to make sure that none of the values that were read were set to zeros + FAPI_ASSERT((l_volt_util_active != 0) && + (l_volt_slope != 0) && + (l_volt_intercept != 0) && + (l_vddr_max_limit_mv != 0), + fapi2::CEN_MSS_VOLT_VDDR_OFFSET_VALUE_ERROR() + .set_CEN_TARGET(i_targets[0]) + .set_VDDR_UTIL_ACTIVE(l_volt_util_active) + .set_VDDR_SLOPE(l_volt_slope) + .set_VDDR_INTERCEPT(l_volt_intercept) + .set_VDDR_MAX_LIMIT(l_vddr_max_limit_mv), + "%s One or more dynamic VDD attributes is 0 slope_util_active %lu slope %lu slope_intercept %lu! Exiting....", + mss::c_str(i_targets[0]), l_volt_util_active, l_volt_slope, l_volt_intercept); + + // Print to check the calculation + FAPI_INF("l_data_bus_util %d per 10k l_volt_util_active: %d per 10k l_volt_util_inactive: %d per 10k", + l_data_bus_util, l_volt_util_active, l_volt_util_inactive); + + + l_num_dimms_to_add = 1; + + // Computes the preliminary VDDR value + for(const auto& l_chip : i_targets) + { + // Gets the functional attribute to check for an active centaur + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUNCTIONAL, l_chip, l_is_functional)); + + // Gets the power slope values and does error checks if this card is functional, as it should have good VPD. if the card is non-functional, continue using good VPD power slope values + auto l_rc = FAPI_ATTR_GET(fapi2::ATTR_CEN_CDIMM_VPD_MASTER_POWER_SLOPE, l_chip, l_vpd_master_power_slope); + + if(l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + { + FAPI_TRY(l_rc); + } + + l_rc = FAPI_ATTR_GET(fapi2::ATTR_CEN_CDIMM_VPD_MASTER_POWER_INTERCEPT, l_chip, l_vpd_master_power_intercept); + + if(l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) + { + FAPI_TRY(l_rc); + } + + // Removes leading bits from the VPD MASTER POWER attributes, leaving only the values needed for the power calculations + l_vpd_master_power_slope &= 0x1FFF; + l_vpd_master_power_intercept &= 0x1FFF; + + // Checks to make sure that the attribute values are non-zero - calls out all bad DIMMs + if(((l_vpd_master_power_slope * l_vpd_master_power_intercept) == 0) + && (l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL)) + { + FAPI_ASSERT((l_volt_util_active != 0) && + (l_volt_slope != 0) && + (l_volt_intercept != 0), + fapi2::CEN_MSS_VOLT_VDDR_OFFSET_VPD_VALUE_ERROR() + .set_CEN_TARGET(i_targets[0]) + .set_VPD_MASTER_POWER_SLOPE(l_vpd_master_power_slope) + .set_VPD_MASTER_POWER_INTERCEPT(l_vpd_master_power_intercept), + "%s One or more VPD Power slope attributes is 0. Logging error and looking for additional bad DIMMs. power_slope %lu power_intercept %lu! Exiting....", + mss::c_str(i_targets[0]), l_vpd_master_power_slope, l_vpd_master_power_intercept); + + // Using a generic error here as we already logged the other error above + l_bad_vpd_rc = fapi2::FAPI2_RC_INVALID_PARAMETER; + continue; + } + // One or more DIMM has already been called out, skip doing the calculation and continue to try to find bad DIMMs + else if(l_bad_vpd_rc) + { + FAPI_INF("Already found a bad DIMM. Skipping calculations on this DIMM."); + continue; + } + // Has not found good master_power_slopes and has bad master power slopes + else if(((l_good_master_power_slope == 0) || (l_good_master_power_intercept == 0)) && + ((l_vpd_master_power_slope == 0) || (l_vpd_master_power_intercept == 0))) + { + l_num_dimms_to_add++; + FAPI_INF("Found bad l_vpd_master_power_slope or l_vpd_master_power_intercept values on non-functional DIMM. Program has not found good values yet, adding one more DIMM to run when good values are found. Currently going to run %d DIMMs in the next dimm.", + l_num_dimms_to_add); + continue; + } + // Found bad master power slope or power intercept but has good master power slope or intercepts + else if(((l_vpd_master_power_slope == 0) || (l_vpd_master_power_intercept == 0)) && + ((l_good_master_power_slope > 0) && (l_good_master_power_intercept > 0))) + { + // Uses assumed (last good master power slope and intercept) values for these calculations + FAPI_INF("Found bad l_vpd_master_power_slope or l_vpd_master_power_intercept values on non-functional DIMM. Program is using the last good values for the calculations for this DIMM."); + l_vpd_master_power_slope = l_good_master_power_slope; + l_vpd_master_power_intercept = l_good_master_power_intercept; + } + // Found good master power slopes -> set the good master power slope values + else if((l_vpd_master_power_slope > 0) && (l_vpd_master_power_intercept > 0 )) + { + l_good_master_power_slope = l_vpd_master_power_slope; + l_good_master_power_intercept = l_vpd_master_power_intercept; + } + + // Loops through all MBA chiplets to compare the compute the total number of logical dimms associated with a centaur + l_num_logical_dimms = 0; + + for(const auto& l_mba : mss::find_targets<fapi2::TARGET_TYPE_MBA>(l_chip)) + { + l_num_logical_dimms += mss::count_dimm(l_mba); + }//end for + + // Multiply by total number of active logical dimms + { + // Temporary variables to compress the functions below + const bool l_functional = l_is_functional == fapi2::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL; + const auto l_volt_util = l_functional ? l_volt_util_active : l_volt_util_inactive; + + // Calculates the uplift percentage + const auto UPLIFT = (PERCENT + l_percent_uplift) / PERCENT; + // Note: static cast makes the entire calcuation a floating point calculation, which is what we want + // Calculates the power usage per active DIMM + const auto POWER_CURVE = (static_cast<double>(l_vpd_master_power_slope) * l_volt_util / ATTR_VOLT_CONVERSION) + + l_vpd_master_power_intercept; + + // Calculates the power on VDDR + l_var_power_on_vddr += static_cast<uint32_t>(l_num_dimms_to_add * POWER_CURVE * l_num_logical_dimms * UPLIFT); + FAPI_INF("%s l_var_power_on_vddr: %d cW l_vpd_master_power_slope: %d cW l_volt_util_%sactive: %d per 10k l_vpd_master_power_intercept %d cW l_num_logical_dimms %d l_percent_uplift %d %%", + mss::c_str(l_chip), l_var_power_on_vddr, l_vpd_master_power_slope, l_functional ? "" : "in", + l_volt_util_active, l_vpd_master_power_intercept, l_num_logical_dimms, l_percent_uplift); + } + + // Resets the number of DIMMs to add. + l_num_dimms_to_add = 1; + }//end for + + // Found a bad DIMM, exit + FAPI_TRY(l_bad_vpd_rc, "Found one or more functional DIMM with bad VPD. Exiting...."); + + // Debug print + FAPI_INF("l_var_power_on_vddr: %d cW l_volt_slope: %d uV/W l_volt_intercept: %d mV", + l_var_power_on_vddr, l_volt_slope, l_volt_intercept); + + // Computes and converts the voltage offset into mV + // Naked numbers are for this calculation and are a one to one port from the p8 code base + l_param_vddr_voltage_mv = (500 + l_var_power_on_vddr * l_volt_slope / 100) / 1000 + l_volt_intercept; + FAPI_INF("l_param_vddr_voltage_mv: %d mV", l_param_vddr_voltage_mv); + + // Found that the VDDR voltage is over the maximum limit + if(l_param_vddr_voltage_mv > l_vddr_max_limit_mv) + { + FAPI_INF("l_param_vddr_voltage_mv, %d mV, is over l_vddr_max_limit_mv of %d mV.", l_param_vddr_voltage_mv, + l_vddr_max_limit_mv); + FAPI_INF("Setting l_param_vddr_voltage_mv to l_vddr_max_limit_mv"); + l_param_vddr_voltage_mv = l_vddr_max_limit_mv; + } + + // Prints out the final attribute value + FAPI_INF("ATTR_CEN_MSS_VDDR_OFFSET: %d mV", l_param_vddr_voltage_mv); + + // Sets the output attributes + for(const auto& l_chip : i_targets) + { + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_MSS_VDDR_OFFSET, l_chip, l_param_vddr_voltage_mv)); + }//end for + + fapi_try_exit: + return fapi2::current_err; + } + +} // extern "C" diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.H index e6b9ba9b5..e34e26d20 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.H @@ -22,3 +22,34 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// @file p9c_mss_mss_volt_vddr_offset.H +/// @brief Creates VDDR voltage offsets +/// +/// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +/// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 3 +/// *HWP Consumed by: HB + +#ifndef P9C_MSS_VOLT_VDDR_OFFSET_H +#define P9C_MSS_VOLT_VDDR_OFFSET_H + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9c_mss_volt_vddr_offset_FP_t)(const + std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>>&); + +extern "C" +{ + + /// + /// @brief mss_volt_vddr_offset procedure. Determines operating vddr voltage for dimms behind a vddr voltage domain + /// @param[in] i_targets Reference to vector of Centaur Targets in a particular vddr power domain + /// @return ReturnCode + /// + + fapi2::ReturnCode p9c_mss_volt_vddr_offset(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>>& i_targets); + +} // extern "C" + +#endif // P9C_MSS_VOLT_VDDR_OFFSET_H diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml index 80656eb1d..d87aae99b 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/centaur_ec_attributes.xml @@ -489,7 +489,6 @@ The getMBvpdSlopeInterceptData Attribute Accessor, if it does not find a matchin </chipEcFeature> </attribute> -<!-- <attribute> <id>ATTR_CEN_CENTAUR_EC_FEATURE_DISABLE_VDDR_DYNAMIC_VID</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -506,7 +505,6 @@ The getMBvpdSlopeInterceptData Attribute Accessor, if it does not find a matchin </chip> </chipEcFeature> </attribute> ---> <!-- ********************************************************************* --> diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml index 012be2b73..5c1ad1fb9 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/memory_attributes.xml @@ -27,8 +27,8 @@ <!-- @file memory_attributes.xml --> <!-- @brief Attribute xml for memory attributes --> <!-- --> -<!-- *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> --> -<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> +<!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> +<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> --> <!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> <!-- *HWP Team: Memory --> <!-- *HWP Level: 2 --> @@ -3147,66 +3147,6 @@ Will be set at an MBA level with one policy to be used</description> <!-- <attribute> - <id>ATTR_CEN_MSS_AVDD_OFFSET_DISABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for to determine whether to apply an offset to AVDD. Supplied by MRW.</description> - <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> - <platInit/> - <odmVisable/> -</attribute> ---> - -<!-- -<attribute> - <id>ATTR_CEN_MSS_VDD_OFFSET_DISABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for to determine whether to apply an offset to VDD. Supplied by MRW.</description> - <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> - <platInit/> - <odmVisable/> -</attribute> ---> - -<!-- -<attribute> - <id>ATTR_CEN_MSS_VCS_OFFSET_DISABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description> - <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> - <platInit/> - <odmVisable/> -</attribute> ---> - -<!-- -<attribute> - <id>ATTR_CEN_MSS_VPP_OFFSET_DISABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description> - <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> - <platInit/> - <odmVisable/> -</attribute> ---> - -<!-- -<attribute> - <id>ATTR_CEN_MSS_VDDR_OFFSET_DISABLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>Used for to determine whether to apply an offset to VDDR. Supplied by MRW.</description> - <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> - <platInit/> - <odmVisable/> -</attribute> ---> - -<!-- -<attribute> <id>ATTR_CEN_MSS_AVDD_SLOPE_ACTIVE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Slope value used to determine the dynamic VID AVDD adjustment for ACTIVE parts. In uV/Centaur.</description> @@ -3326,7 +3266,6 @@ Will be set at an MBA level with one policy to be used</description> </attribute> --> -<!-- <attribute> <id>ATTR_CEN_MSS_DDR3_VDDR_SLOPE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3334,10 +3273,9 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x000000FA</default> </attribute> ---> -<!-- <attribute> <id>ATTR_CEN_MSS_DDR3_VDDR_INTERCEPT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3345,10 +3283,9 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x00000556</default> </attribute> ---> -<!-- <attribute> <id>ATTR_CEN_MSS_DDR4_VDDR_SLOPE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3356,10 +3293,9 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x000000FA</default> </attribute> ---> -<!-- <attribute> <id>ATTR_CEN_MSS_DDR4_VDDR_INTERCEPT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3367,8 +3303,8 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x000004C4</default> </attribute> ---> <attribute> <id>ATTR_CEN_MSS_VOLT_OVERRIDE</id> @@ -3390,7 +3326,7 @@ Will be set at an MBA level with one policy to be used</description> <odmVisable/> </attribute> -<!-- + <attribute> <id>ATTR_CEN_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> <targetType>TARGET_TYPE_SYSTEM</targetType> @@ -3400,8 +3336,9 @@ Will be set at an MBA level with one policy to be used</description> <odmVisable/> <odmChangeable/> </attribute> ---> + +<!-- Dynamic voltage attributes below are commented out as they are unneeded for the current code --> <!-- <attribute> <id>ATTR_CEN_MSS_AVDD_OFFSET</id> @@ -3446,7 +3383,6 @@ Will be set at an MBA level with one policy to be used</description> </attribute> --> -<!-- <attribute> <id>ATTR_CEN_MSS_VDDR_OFFSET</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3455,7 +3391,6 @@ Will be set at an MBA level with one policy to be used</description> <writeable/> <odmVisable/> </attribute> ---> <!-- <attribute> @@ -3504,7 +3439,6 @@ Will be set at an MBA level with one policy to be used</description> </attribute> --> -<!-- <attribute> <id>ATTR_CEN_MRW_DDR3_VDDR_MAX_LIMIT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3512,10 +3446,9 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x00000591</default> </attribute> ---> -<!-- <attribute> <id>ATTR_CEN_MRW_DDR4_VDDR_MAX_LIMIT</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -3523,8 +3456,8 @@ Will be set at an MBA level with one policy to be used</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> + <default>0x000004f6</default> </attribute> ---> <attribute> <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id> @@ -3566,4 +3499,5 @@ Will be set at an MBA level with one policy to be used</description> <persistRuntime/> </attribute> --> + </attributes> diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_volt_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_volt_errors.xml index 76cfb5643..189bfa36f 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_volt_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_volt_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -27,8 +27,8 @@ <!-- @file p9c_memory_mss_volt_errors.xml --> <!-- @brief Error xml for mss volt errors--> <!-- --> -<!-- *HWP HWP Owner: Luke Mulkey <lwmulkey@us.ibm.com> --> -<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> --> +<!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> +<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> --> <!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> <!-- *HWP Team: Memory --> <!-- *HWP Level: 1 --> @@ -117,5 +117,77 @@ </callout> </hwpError> + <hwpError> + <rc>RC_CEN_MSS_VDDR_FUNCTIONAL_DIMM_VPD_READ_ERROR</rc> + <description>Unable to read the VPD from a non-functional dimm.</description> + <ffdc>DIMM_TARGET</ffdc> + <ffdc>MBA_TARGET</ffdc> + <callout> + <target>MBA_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <target>DIMM_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MBA_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_CEN_MSS_VOLT_VDDR_OFFSET_DRAM_GEN_MISCOMPARE</rc> + <description>One or more DIMMs has a different generation of DRAM technology level.</description> + <ffdc>DRAM_GEN_MISCOMPARE</ffdc> + <ffdc>DRAM_GEN_START</ffdc> + <ffdc>MBA_TARGET</ffdc> + <ffdc>DIMM_TARGET</ffdc> + </hwpError> + + <hwpError> + <rc>RC_CEN_MSS_VOLT_VDDR_FUNCTIONAL_CENTAUR_NOT_FOUND</rc> + <description>Code did not find a functional centaur.</description> + <ffdc>CEN_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_CEN_MSS_VOLT_VDDR_DRAM_GEN_NOT_FOUND</rc> + <description>Code did not find a DIMM with a readable attribute for DRAM_GEN.</description> + <ffdc>CEN_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_CEN_MSS_VOLT_VDDR_OFFSET_VALUE_ERROR</rc> + <ffdc>VDDR_UTIL_ACTIVE</ffdc> + <ffdc>VDDR_SLOPE</ffdc> + <ffdc>VDDR_INTERCEPT</ffdc> + <ffdc>CEN_TARGET</ffdc> + <ffdc>VDDR_MAX_LIMIT</ffdc> + <description>One or more dynamic VDDR attributes is 0.</description> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_CEN_MSS_VOLT_VDDR_OFFSET_VPD_VALUE_ERROR</rc> + <description>one or more VPD voltage attributes is 0.</description> + <ffdc>VPD_MASTER_POWER_SLOPE</ffdc> + <ffdc>VPD_MASTER_POWER_INTERCEPT</ffdc> + <ffdc>CEN_TARGET</ffdc> + <deconfigure> + <target>CEN_TARGET</target> + </deconfigure> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 09537972f..1ee63867f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -21062,101 +21062,101 @@ fapi_try_exit: } /// -/// @brief ATTR_MSS_MRW_AVDD_OFFSET_DISABLE getter +/// @brief ATTR_MSS_MRW_AVDD_OFFSET_ENABLE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Used for to determine whether to apply an offset to AVDD. Supplied by /// MRW. /// -inline fapi2::ReturnCode mrw_avdd_offset_disable(uint8_t& o_value) +inline fapi2::ReturnCode mrw_avdd_offset_enable(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_AVDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_AVDD_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_AVDD_OFFSET_DISABLE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_AVDD_OFFSET_ENABLE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_VDD_OFFSET_DISABLE getter +/// @brief ATTR_MSS_MRW_VDD_OFFSET_ENABLE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Used for to determine whether to apply an offset to VDD. Supplied by /// MRW. /// -inline fapi2::ReturnCode mrw_vdd_offset_disable(uint8_t& o_value) +inline fapi2::ReturnCode mrw_vdd_offset_enable(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDD_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDD_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_VDD_OFFSET_DISABLE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_VDD_OFFSET_ENABLE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_VCS_OFFSET_DISABLE getter +/// @brief ATTR_MSS_MRW_VCS_OFFSET_ENABLE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Used for to determine whether to apply an offset to VCS. Supplied by /// MRW. /// -inline fapi2::ReturnCode mrw_vcs_offset_disable(uint8_t& o_value) +inline fapi2::ReturnCode mrw_vcs_offset_enable(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VCS_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VCS_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_VCS_OFFSET_DISABLE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_VCS_OFFSET_ENABLE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_VPP_OFFSET_DISABLE getter +/// @brief ATTR_MSS_MRW_VPP_OFFSET_ENABLE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Used for to determine whether to apply an offset to VCS. Supplied by /// MRW. /// -inline fapi2::ReturnCode mrw_vpp_offset_disable(uint8_t& o_value) +inline fapi2::ReturnCode mrw_vpp_offset_enable(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VPP_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VPP_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_VPP_OFFSET_DISABLE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_VPP_OFFSET_ENABLE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_VDDR_OFFSET_DISABLE getter +/// @brief ATTR_MSS_MRW_VDDR_OFFSET_ENABLE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Used for to determine whether to apply an offset to VDDR. Supplied by /// MRW. /// -inline fapi2::ReturnCode mrw_vddr_offset_disable(uint8_t& o_value) +inline fapi2::ReturnCode mrw_vddr_offset_enable(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDDR_OFFSET_DISABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_VDDR_OFFSET_ENABLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_VDDR_OFFSET_DISABLE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_VDDR_OFFSET_ENABLE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 7496bbe17..48ecc68d8 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -335,63 +335,63 @@ </attribute> <attribute> - <id>ATTR_MSS_MRW_AVDD_OFFSET_DISABLE</id> + <id>ATTR_MSS_MRW_AVDD_OFFSET_ENABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Used for to determine whether to apply an offset to AVDD. Supplied by MRW.</description> <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> + <enum>ENABLE = 1, DISABLE = 0</enum> <platInit/> <initToZero/> <!-- little comment to tell us this might change during power/thermal implemetation --> - <mssAccessorName>mrw_avdd_offset_disable</mssAccessorName> + <mssAccessorName>mrw_avdd_offset_enable</mssAccessorName> </attribute> <attribute> - <id>ATTR_MSS_MRW_VDD_OFFSET_DISABLE</id> + <id>ATTR_MSS_MRW_VDD_OFFSET_ENABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Used for to determine whether to apply an offset to VDD. Supplied by MRW.</description> <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> + <enum>ENABLE = 1, DISABLE = 0</enum> <platInit/> <initToZero/> <!-- little comment to tell us this might change during power/thermal implemetation --> - <mssAccessorName>mrw_vdd_offset_disable</mssAccessorName> + <mssAccessorName>mrw_vdd_offset_enable</mssAccessorName> </attribute> <attribute> - <id>ATTR_MSS_MRW_VCS_OFFSET_DISABLE</id> + <id>ATTR_MSS_MRW_VCS_OFFSET_ENABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description> <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> + <enum>ENABLE = 1, DISABLE = 0</enum> <platInit/> <initToZero/> <!-- little comment to tell us this might change during power/thermal implemetation --> - <mssAccessorName>mrw_vcs_offset_disable</mssAccessorName> + <mssAccessorName>mrw_vcs_offset_enable</mssAccessorName> </attribute> <attribute> - <id>ATTR_MSS_MRW_VPP_OFFSET_DISABLE</id> + <id>ATTR_MSS_MRW_VPP_OFFSET_ENABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Used for to determine whether to apply an offset to VCS. Supplied by MRW.</description> <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> + <enum>ENABLE = 1, DISABLE = 0</enum> <platInit/> <initToZero/> <!-- little comment to tell us this might change during power/thermal implemetation --> - <mssAccessorName>mrw_vpp_offset_disable</mssAccessorName> + <mssAccessorName>mrw_vpp_offset_enable</mssAccessorName> </attribute> <attribute> - <id>ATTR_MSS_MRW_VDDR_OFFSET_DISABLE</id> + <id>ATTR_MSS_MRW_VDDR_OFFSET_ENABLE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Used for to determine whether to apply an offset to VDDR. Supplied by MRW.</description> <valueType>uint8</valueType> - <enum>DISABLE = 1, ENABLE = 0</enum> + <enum>ENABLE = 1, DISABLE = 0</enum> <platInit/> <initToZero/> <!-- little comment to tell us this might change during power/thermal implemetation --> - <mssAccessorName>mrw_vddr_offset_disable</mssAccessorName> + <mssAccessorName>mrw_vddr_offset_enable</mssAccessorName> </attribute> <attribute> diff --git a/src/import/generic/memory/lib/utils/find.H b/src/import/generic/memory/lib/utils/find.H index 3ba3b757e..c73b49619 100644 --- a/src/import/generic/memory/lib/utils/find.H +++ b/src/import/generic/memory/lib/utils/find.H @@ -243,6 +243,26 @@ find_targets( const fapi2::Target<fapi2::TARGET_TYPE_DMI>& i_target ) } /// +/// @brief find all the DIMM connected to a centaur +/// @param[in] i_target a fapi2::Target TARGET_TYPE_MEMBUF_CHIP +/// @return a vector of fapi2::TARGET_TYPE_DIMM +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > +find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target ) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > l_dimms; + + for (const auto& l_mba : i_target.getChildren<fapi2::TARGET_TYPE_MBA>()) + { + auto l_these_dimms( l_mba.getChildren<fapi2::TARGET_TYPE_DIMM>() ); + l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); + } + + return l_dimms; +} + +/// /// @brief find all the dimm connected to an MCS /// @param[in] i_target a fapi2::Target MCS /// @return a vector of fapi2::TARGET_TYPE_DIMM |