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authorThi Tran <thi@us.ibm.com>2017-08-28 09:28:59 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-12-10 15:57:04 -0500
commitedbb12014deb2947fc6a633691d6a0816e7b4c21 (patch)
tree7b3ff8aec0f37551fad0380e5ca2bae5fd01dd91
parentd3ecbc6808176aa9a73c9fb94470028f67633f05 (diff)
downloadtalos-hostboot-edbb12014deb2947fc6a633691d6a0816e7b4c21.tar.gz
talos-hostboot-edbb12014deb2947fc6a633691d6a0816e7b4c21.zip
L3 update - p9_cme_sram_access HWP
Change-Id: Icddd9086b3b09f281a2323bcda3c5e417ffdd658 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45223 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50671 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.C59
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.H13
2 files changed, 16 insertions, 56 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.C b/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.C
index 25404108d..a2e18cdf9 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.C
@@ -22,60 +22,35 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
+
///
/// @file p9_cme_sram_access.C
/// @brief Display data from the targetted CME's SRAM array.
-
+///
// *HWP HWP Owner : Brian Vanderpool <vanderp@us.ibm.com>
// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
-// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
// *HWP Team : PM
-// *HWP Level : 2
+// *HWP Level : 3
// *HWP Consumed by : HS:CRO:SBE
///
-///-----------------------------------------------------------------------------
-
-///
-/// High-level procedure flow:
-/// @verbatim
-/// High-level procedure flow:
-///
-///
-/// @endverbatim
// -----------------------------------------------------------------------------
// Includes
// -----------------------------------------------------------------------------
#include <p9_cme_sram_access.H>
-
-
+#include <p9_quad_scom_addresses.H>
// ----------------------------------------------------------------------
// Constants
// ----------------------------------------------------------------------
-
const uint8_t CSCR_AUTO_INCREMENT_BIT = 0;
-
-// -----------------------------------------------------------------------------
-// Function prototypes
-// -----------------------------------------------------------------------------
-
// -----------------------------------------------------------------------------
// Function definitions
// -----------------------------------------------------------------------------
-/// @brief Dump the contents of the CME SRAM
-///
-/// @param [in] i_cme_target EX target
-/// @param [in] i_start_address Start Address is between 0xFFFF80000 and 0xFFFFFFFF and must be 8B aligned
-/// @param [in] i_length_dword Length in dwords (# of accesses)
-/// @param [out] o_data Output Data
-/// @param [out] o_dwords_read Number of actual words in the output buffer.
-///
-/// @retval FAPI_RC_SUCCESS
-/// @retval ERROR defined in xml
-
+/// See doxygen in header file
fapi2::ReturnCode p9_cme_sram_access(
const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_cme_target,
const uint32_t i_start_address,
@@ -83,7 +58,6 @@ fapi2::ReturnCode p9_cme_sram_access(
uint64_t* o_data,
uint32_t& o_dwords_read)
{
-
fapi2::buffer<uint64_t> l_data64;
// These are initialized before being used.
@@ -91,16 +65,14 @@ fapi2::ReturnCode p9_cme_sram_access(
uint32_t l_norm_address;
uint32_t l_words_to_read;
-
- FAPI_IMP("> p9_cme_sram_access");
+ FAPI_DBG("> p9_cme_sram_access");
// Ensure the address is between 0xFFFF8000 and 0xFFFFFFFF.
// No need to check the upper limit, since that will overflow the uint32_t data type.
-
if (i_start_address < 0xFFFF8000)
{
// Return Error - invalid start address
- FAPI_DBG("Invalid Start Address %08X", i_start_address);
+ FAPI_DBG("Invalid Start Address 0x%.8X", i_start_address);
FAPI_ASSERT(false,
fapi2::CME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
"Invalid CME Start address");
@@ -109,28 +81,23 @@ fapi2::ReturnCode p9_cme_sram_access(
if ((i_start_address & 0x00000007) != 0)
{
// Return Error - invalid start address alignment
- FAPI_DBG("Invalid Start Address alignment %08X", i_start_address);
+ FAPI_DBG("Invalid Start Address alignment 0x%.8X", i_start_address);
FAPI_ASSERT(false,
fapi2::CME_SRAM_ACCESS_ERROR().set_ADDRESS(i_start_address),
"Invalid CME Start address alignment");
}
-
// Enable auto increment
FAPI_INF(" CME display enable auto increment mode");
l_data64.flush<0>().setBit<CSCR_AUTO_INCREMENT_BIT>();
FAPI_TRY(fapi2::putScom(i_cme_target, EX_CSCR_OR, l_data64), "Error enabling auto increment mode");
-
-
// Set the CME address
// The SRAM address is defined as 16:28 (64k) but the CME only supports 32k, so mask off bit 16
-
l_norm_address = i_start_address & 0x00007FF8;
-
l_data64 = ((uint64_t)(l_norm_address)) << 32;
- FAPI_DBG(" CME Setting Read address (CSAR) to 0x%08X", l_data64);
+ FAPI_DBG(" CME Setting Read address (CSAR) to 0x%.16llX", l_data64);
FAPI_TRY(fapi2::putScom(i_cme_target, EX_CSAR, l_data64), "Error setting read address in CSR");
// Compute the number of words
@@ -143,7 +110,7 @@ fapi2::ReturnCode p9_cme_sram_access(
l_words_to_read = i_length_dword;
}
- FAPI_DBG(" Reading %d words From 0x%08X to 0x%08X", l_words_to_read, l_norm_address,
+ FAPI_DBG(" Reading %d words From 0x%.8X to 0x%.8X", l_words_to_read, l_norm_address,
l_norm_address + l_words_to_read * 8);
// o_dwords_read will indicate the number of words successfully read. Increment after each read.
@@ -156,9 +123,7 @@ fapi2::ReturnCode p9_cme_sram_access(
o_dwords_read++;
}
-
-
fapi_try_exit:
- FAPI_INF("< p9_cme_sram_access");
+ FAPI_DBG("< p9_cme_sram_access");
return fapi2::current_err;
}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.H b/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.H
index 7b64df928..f73ad5f8e 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_cme_sram_access.H
@@ -23,16 +23,18 @@
/* */
/* IBM_PROLOG_END_TAG */
///
+
/// @file p9_cme_sram_access.H
/// @brief Display data from the targetted CME's SRAM array.
///
// *HWP HWP Owner : Brian Vanderpool <vanderp@us.ibm.com>
// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
-// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
// *HWP Team : PM
-// *HWP Level : 2
+// *HWP Level : 3
// *HWP Consumed by : HS:CRO:SBE
///
+
///-----------------------------------------------------------------------------
#ifndef _p9_cme_sram_access_H_
@@ -41,12 +43,7 @@
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
-
#include <fapi2.H>
-#include <p9_quad_scom_addresses.H>
-
-#include <p9_pm.H>
-
// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_cme_sram_access_FP_t) (
@@ -58,7 +55,6 @@ typedef fapi2::ReturnCode (*p9_cme_sram_access_FP_t) (
extern "C" {
-
// -----------------------------------------------------------------------------
// Function prototype
// -----------------------------------------------------------------------------
@@ -81,7 +77,6 @@ extern "C" {
/// @param [in] i_length_dword Length in dwords (# of accesses)
/// @param [out] o_data Output Data
/// @param [out] o_dwords_read Number of actual words in the output buffer.
-
///
/// @retval FAPI2_RC_SUCCESS
/// @retval RC_PROCPM_GPE_CODE_BAD_MODE
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