Level 3 : OCB & OCC procedures

Change-Id: I9c41fbb577680070742549f9ba9aec764ce0516c
RTC: 172617
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39636
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39640
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

13 files changed, 291 insertions, 135 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
index 60131f2a0..7ca25f236 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -29,8 +29,8 @@
 // *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
 // *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team            : PM
-// *HWP Level           : 2
-// *HWP Consumed by     : FSP:HS
+// *HWP Level           : 3
+// *HWP Consumed by     : SBE:HS
 
 ///
 /// High-level procedure flow:
@@ -60,6 +60,10 @@ enum
     OCB_FULL_POLL_DELAY_SIM = 0
 };
 
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+
 fapi2::ReturnCode p9_pm_ocb_indir_access(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     const p9ocb::PM_OCB_CHAN_NUM  i_ocb_chan,
@@ -134,12 +138,15 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
         FAPI_TRY(fapi2::putScom(i_target, l_OCBAR_address, l_data64));
     }
 
-    // PUT Operation
+    // PUT Operation: Write data to the SRAM in the given location
+    //                via the OCB channel
     if ( i_ocb_op == p9ocb::OCB_PUT )
     {
         FAPI_INF("OCB access for data write operation");
         FAPI_ASSERT(io_ocb_buffer != NULL,
-                    fapi2::PM_OCB_PUT_NO_DATA_ERROR(),
+                    fapi2::PM_OCB_PUT_NO_DATA_ERROR().
+                    set_CHANNEL(i_ocb_chan).
+                    set_DATA_SIZE(i_ocb_req_length),
                     "No data provided for PUT operation");
 
         fapi2::buffer<uint64_t> l_data64;
@@ -186,7 +193,9 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
 
                 FAPI_ASSERT((true == l_push_ok_flag),
                             fapi2::PM_OCB_PUT_DATA_POLL_NOT_FULL_ERROR().
-                            set_PUSHQ_STATE(l_data64),
+                            set_CHANNEL(i_ocb_chan).
+                            set_DATA_SIZE(i_ocb_req_length).
+                            set_TARGET(i_target),
                             "Polling timeout waiting on push non-full");
             }
         }
@@ -196,6 +205,13 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
         for(uint32_t l_index = 0; l_index < i_ocb_req_length; l_index++)
         {
             l_data64.insertFromRight(io_ocb_buffer[l_index], 0, 64);
+            /* The data read is done via this getscom operation.
+             * A data write failure will be logged off as a simple scom failure.
+             * Need to find a way to distiniguish this error and collect
+             * additional information incase of a failure.*/
+            // @TODO RTC 173286 - FAPI2:  FAPI_TRY (or surrogate name)
+            //                    that allows access to the return code for
+            //                    HWP reaction
             FAPI_TRY(fapi2::putScom(i_target, l_OCBDR_address, l_data64),
                      "ERROR:Failed to complete write to channel data register");
             o_ocb_act_length++;
@@ -205,7 +221,7 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
 
         FAPI_DBG("%d blocks(64bits each) of data put", o_ocb_act_length);
     }
-    // GET Operation
+    // GET Operation: Data read from the given location in SRAM via OCB channel
     else if( i_ocb_op == p9ocb::OCB_GET )
     {
         FAPI_INF("OCB access for data read operation");
@@ -213,9 +229,17 @@ fapi2::ReturnCode p9_pm_ocb_indir_access(
         fapi2::buffer<uint64_t> l_data64;
         uint64_t l_data = 0;
 
+        // Read data from the Channel Data Register in blocks of 64 bits.
         for (uint32_t l_loopCount = 0; l_loopCount < i_ocb_req_length;
              l_loopCount++)
         {
+            /* The data read is done via this getscom operation.
+             * A data read failure will be logged off as a simple scom failure.
+             * Need to find a way to distiniguish this error and collect
+             * additional information incase of a failure.*/
+            // @TODO RTC 173286 - FAPI2:  FAPI_TRY (or surrogate name)
+            //                    that allows access to the return code for
+            //                    HWP reaction
             FAPI_TRY(fapi2::getScom(i_target, l_OCBDR_address, l_data64),
                      "ERROR: Failed to read data from channel %d", i_ocb_chan);
             l_data64.extract(l_data, 0, 64);
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H
index a3ce52b0d..780e9818e 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -31,8 +31,8 @@
 // *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
 // *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team            : PM
-// *HWP Level           : 2
-// *HWP Consumed by     : FSP:HS
+// *HWP Level           : 3
+// *HWP Consumed by     : SBE:HS
 
 #ifndef _P9_PM_OCB_INDIR_ACCESS_H_
 #define _P9_PM_OCB_INDIR_ACCESS_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C
index 8b139ae2b..52d4b4ad0 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -26,14 +26,13 @@
 /// @file  p9_pm_ocb_init.C
 /// @brief Setup and configure OCB channels
 ///
-// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
-// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
-// *HWP Team: PM
-// *HWP Level: 2
-// *HWP Consumed by: FSP:HS
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 3
+// *HWP Consumed by     : SBE:HS
 
-///   Add support for linear window mode
-///
 ///   High-level procedure flow:
 ///
 ///   - if mode = PM_INIT
@@ -293,7 +292,9 @@ fapi2::ReturnCode pm_ocb_setup(
             FAPI_ASSERT(
                 false,
                 fapi2::PM_OCBINIT_BAD_Q_LENGTH_PARM().
-                set_BADQLENGTH(i_ocb_q_len),
+                set_BADQLENGTH(i_ocb_q_len).
+                set_CHANNEL(i_ocb_chan).
+                set_TYPE(i_ocb_type),
                 "ERROR: Bad Queue Length Passed to Procedure => %d",
                 i_ocb_q_len);
         }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
index bbe404dbb..174a531ef 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,11 @@
 /// @brief Setup and configure OCB channels
 ///
 // *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
 // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team: PM
-// *HWP Level: 2
-// *HWP Consumed by: FSP:HS
+// *HWP Level: 3
+// *HWP Consumed by: SBE:HS
 
 #ifndef _P9_PM_OCB_INIT_H_
 #define _P9_PM_OCB_INIT_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
index 406b20013..6c778570f 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,11 @@
 /// @brief Initialize boot vector registers and control PPC405
 ///
 // *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>
+// *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
 // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team: PM
-// *HWP Level: 2
-// *HWP Consumed by: FSP:HS
+// *HWP Level: 3
+// *HWP Consumed by: HS
 
 // -----------------------------------------------------------------------------
 //  Includes
@@ -42,9 +43,11 @@
 #include <p9_pm_ocb_indir_access.H>
 #include <p9_pm_utils.H>
 
-/**
- * @brief enumerates opcodes for few instructions.
- */
+// ----------------------------------------------------------------------------
+// Constant definitions
+// ----------------------------------------------------------------------------
+//
+/// @brief enumerates opcodes for few instructions.
 enum
 {
     ORI_OPCODE        = 24,
@@ -62,15 +65,43 @@ enum
     OCC_MEM_BOOT_PGMADDR = 0xFFF40000,
 };
 
-//-----------------------------------------------------------------------------
+enum PPC_BRANCH_INSTR
+{
+    // Branch Absolute 0xFFF40002  (boot from sram)
+    PPC405_BRANCH_SRAM_INSTR = 0x4BF40002,
+    // Branch Absolute 0x00000040  (boot from memory)
+    PPC405_BRANCH_MEM_INSTR  = 0x48000042,
+    // Branch Relative -16         (boot from sram)
+    PPC405_BRANCH_OLD_INSTR  = 0x4BFFFFF0
+};
+
+enum DELAY_VALUE
+{
+    NS_DELAY = 1000000,// 1,000,000 ns = 1ms
+    SIM_CYCLE_DELAY = 10000
+};
+
+// OCR Register Bits
+static const uint32_t OCB_PIB_OCR_CORE_RESET_BIT = 0;
+static const uint32_t OCB_PIB_OCR_OCR_DBG_HALT_BIT = 10;
+
+// OCC JTAG Register Bits
+static const uint32_t JTG_PIB_OJCFG_DBG_HALT_BIT = 6;
+
+// OCC LFIR Bits
+static const uint32_t OCCLFIR_PPC405_DBGSTOPACK_BIT = 31;
+
 
-/**
- * @brief generates ori instruction code.
- * @param[in]   i_Rs    Source register number
- * @param[in]   i_Ra    Destination regiser number
- * @param[in]   i_data  16 bit immediate data
- * @return  returns 32 bit instruction representing ori instruction.
- */
+//-----------------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------------
+///
+/// @brief generates ori instruction code.
+/// @param[in]   i_Rs    Source register number
+/// @param[in]   i_Ra    Destination regiser number
+/// @param[in]   i_data  16 bit immediate data
+/// @return  returns 32 bit instruction representing ori instruction.
+///
 uint32_t ppc_ori( const uint16_t i_Rs, const uint16_t i_Ra,
                   const uint16_t i_data )
 {
@@ -83,15 +114,12 @@ uint32_t ppc_ori( const uint16_t i_Rs, const uint16_t i_Ra,
     return oriInstOpcode;
 }
 
-
-//-----------------------------------------------------------------------------
-
-/**
- * @brief generates lis (eg addis to 0) instruction code.
- * @param[in]   i_Rt    Target register number
- * @param[in]   i_data  16 bit immediate data
- * @return  returns 32 bit instruction representing lis instruction.
- */
+///
+/// @brief generates lis (eg addis to 0) instruction code.
+/// @param[in]   i_Rt    Target register number
+/// @param[in]   i_data  16 bit immediate data
+/// @return  returns 32 bit instruction representing lis instruction.
+///
 uint32_t ppc_lis( const uint16_t i_Rt,
                   const uint16_t i_data )
 {
@@ -103,14 +131,11 @@ uint32_t ppc_lis( const uint16_t i_Rt,
     return lisInstOpcode;
 }
 
-
-//-----------------------------------------------------------------------------
-
-/**
- * @brief generates branch absolute instruction code.
- * @param[in]   i_TargetAddr  Target address
- * @return  returns 32 bit instruction representing branch absolute instruction.
- */
+///
+/// @brief generates branch absolute instruction code.
+/// @param[in]   i_TargetAddr  Target address
+/// @return  returns 32 bit instruction representing branch absolute instruction.
+///
 uint32_t ppc_b( const uint32_t i_TargetAddr)
 {
     uint32_t brInstOpcode = 0;
@@ -120,12 +145,10 @@ uint32_t ppc_b( const uint32_t i_TargetAddr)
     return brInstOpcode;
 }
 
-//-----------------------------------------------------------------------------
-
-/**
- * @brief generates branch conditional to count register instruction code.
- * @return  returns 32 bit instruction representing branch absolute instruction.
- */
+///
+/// @brief generates branch conditional to count register instruction code.
+/// @return  returns 32 bit instruction representing branch absolute instruction.
+//
 uint32_t ppc_bctr( )
 {
     uint32_t bctrInstOpcode = 0;
@@ -137,14 +160,12 @@ uint32_t ppc_bctr( )
     return bctrInstOpcode;
 }
 
-//-----------------------------------------------------------------------------
-
-/**
- * @brief generates instruction for mtspr
- * @param[in] i_Rs      source register number
- * @param[in] i_Spr represents spr where data is to be moved.
- * @return returns 32 bit instruction representing mtspr instruction.
- */
+///
+/// @brief generates instruction for mtspr
+/// @param[in] i_Rs      source register number
+/// @param[in] i_Spr represents spr where data is to be moved.
+/// @return returns 32 bit instruction representing mtspr instruction.
+///
 uint32_t ppc_mtspr( const uint16_t i_Rs, const uint16_t i_Spr )
 {
     uint32_t mtsprInstOpcode = 0;
@@ -158,14 +179,13 @@ uint32_t ppc_mtspr( const uint16_t i_Rs, const uint16_t i_Spr )
     return mtsprInstOpcode;
 }
 
-
-/**
- * @brief Creates and loads the OCC memory boot launcher
- * @param[in] i_target  Chip target
- * @param[in] i_data64  32 bit instruction representing the branch
- *                      instruction to the SRAM boot loader
- * @return returns RC
- */
+///
+/// @brief Creates and loads the OCC memory boot launcher
+/// @param[in] i_target  Chip target
+/// @param[in] i_data64  32 bit instruction representing the branch
+///                    instruction to the SRAM boot loader
+/// @return FAPI2_RC_SUCCESS on success, else error
+///
 fapi2::ReturnCode bootMemory(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     fapi2::buffer<uint64_t>& i_data64)
@@ -240,41 +260,6 @@ fapi_try_exit:
 }
 
 
-
-// -----------------------------------------------------------------------------
-//  Constant Defintions
-// -----------------------------------------------------------------------------
-
-enum PPC_BRANCH_INSTR
-{
-    // Branch Absolute 0xFFF40002  (boot from sram)
-    PPC405_BRANCH_SRAM_INSTR = 0x4BF40002,
-    // Branch Absolute 0x00000040  (boot from memory)
-    PPC405_BRANCH_MEM_INSTR  = 0x48000042,
-    // Branch Relative -16         (boot from sram)
-    PPC405_BRANCH_OLD_INSTR  = 0x4BFFFFF0
-};
-
-enum DELAY_VALUE
-{
-    NS_DELAY = 1000000,// 1,000,000 ns = 1ms
-    SIM_CYCLE_DELAY = 10000
-};
-
-// OCR Register Bits
-static const uint32_t OCB_PIB_OCR_CORE_RESET_BIT = 0;
-static const uint32_t OCB_PIB_OCR_OCR_DBG_HALT_BIT = 10;
-
-// OCC JTAG Register Bits
-static const uint32_t JTG_PIB_OJCFG_DBG_HALT_BIT = 6;
-
-// OCC LFIR Bits
-static const uint32_t OCCLFIR_PPC405_DBGSTOPACK_BIT = 31;
-
-
-// -----------------------------------------------------------------------------
-//   Procedure Defintion
-// -----------------------------------------------------------------------------
 fapi2::ReturnCode p9_pm_occ_control
 (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
  const p9occ_ctrl::PPC_CONTROL i_ppc405_reset_ctrl,
@@ -430,7 +415,8 @@ fapi2::ReturnCode p9_pm_occ_control
 
             FAPI_ASSERT (!(l_jtagcfg.getBit<JTG_PIB_OJCFG_DBG_HALT_BIT>()),
                          fapi2::OCC_CONTROL_NONSTART_DUE_TO_RISCWATCH()
-                         .set_JTAGCFG(l_jtagcfg),
+                         .set_JTAGCFG(l_jtagcfg)
+                         .set_TARGET(i_target),
                          "OCC will not start as the JTAG halt from RiscWatch is currently set");
 
             FAPI_INF("Starting the PPC405");
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H
index 1a010f962..7b0f93c1c 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_control.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,11 @@
 /// @brief Reset and halt control of the OCC PPC405
 ///
 // *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>
+// *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
 // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team: PM
-// *HWP Level: 2
-// *HWP Consumed by: FSP:HS
+// *HWP Level: 3
+// *HWP Consumed by: HS
 ///
 /// @verbatim
 /// High-level procedure flow:
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.C
index ed94eb051..bce7ee3d7 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,11 @@
 /// @brief Initialize the SRAM in the OCC
 ///
 // *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
 // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team: PM
-// *HWP Level: 1
-// *HWP Consumed by: FSP:HS
+// *HWP Level: 3
+// *HWP Consumed by: HS
 //
 
 // -----------------------------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.H
index d160dc666..5bce492dc 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_occ_sram_init.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -27,10 +27,11 @@
 /// @brief Initialize the SRAM in the OCC
 ///
 // *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
 // *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
 // *HWP Team: PM
-// *HWP Level: 1
-// *HWP Consumed by: FSP:HS
+// *HWP Level: 3
+// *HWP Consumed by: HS
 //
 
 #ifndef _P9_PM_OCC_SRAM_INIT_H_
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml
index 590f782ee..940b7053d 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -23,14 +23,29 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for p9_pm_ocb_indir_access procedure -->
+<!--
+     *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+     *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
+     *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+     *HWP Team: PM
+     *HWP Level: 3
+     *HWP Consumed by: SBE:HS:FSP
+-->
+
 <hwpErrors>
     <!-- ******************************************************************* -->
     <hwpError>
     <sbeError/>
     <rc>RC_PM_OCB_PUT_NO_DATA_ERROR</rc>
     <description>
-    No data passed for Put operation.
+    Valid data not provided to be written via the OCB channel.
     </description>
+    <ffdc>CHANNEL</ffdc>
+    <ffdc>DATA_SIZE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
     </hwpError>
     <!-- ******************************************************************* -->
     <hwpError>
@@ -41,7 +56,22 @@
     before writing data. Is likely due to OCC firmware not pulling entries off
     of the queue in a timely manner.
     </description>
-    <ffdc>PUSHQ_STATE</ffdc>
+    <ffdc>CHANNEL</ffdc>
+    <ffdc>DATA_SIZE</ffdc>
+    <ffdc>TARGET</ffdc>
+    <collectRegisterFfdc>
+      <id>OCB_CHANNEL_FFDC_REGISTERS</id>
+      <target>TARGET</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    </collectRegisterFfdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <target>TARGET</target>
+      <priority>LOW</priority>
+    </callout>
     </hwpError>
     <!-- ******************************************************************* -->
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml
index 4c42b41be..c89976ee7 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -23,6 +23,14 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for p9_pm_ocb_init procedure -->
+<!--
+     *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+     *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
+     *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+     *HWP Team: PM
+     *HWP Level: 3
+     *HWP Consumed by: SBE:HS:FSP
+-->
 <hwpErrors>
   <!-- ******************************************************************** -->
   <hwpError>
@@ -31,14 +39,25 @@
     <description>Unknown mode passed to p9_pm_ocb_init.
     </description>
     <ffdc>BADMODE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
     <sbeError/>
     <rc>RC_PM_OCBINIT_BAD_Q_LENGTH_PARM</rc>
-    <description>Bad Queue Length Passed to p9_pm_ocb_init.
+    <description>Bad push/pull Queue Length provided while setting
+    up of the OCB channel.
     </description>
     <ffdc>BADQLENGTH</ffdc>
+    <ffdc>CHANNEL</ffdc>
+    <ffdc>TYPE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
   </hwpError>
   <!-- ********************************************************************* -->
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_control_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_control_errors.xml
index fc1a95a4e..a294d81ee 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_control_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_control_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -22,14 +22,15 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-
-<!-- *HWP HWP Owner: Greg Still <stillgs @us.ibm.com>                       -->
-<!-- *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com>                     -->
-<!-- *HWP Team: PM                                                          -->
-<!-- *HWP Level: 1                                                          -->
-<!-- *HWP Consumed by: FSP:HS                                               -->
-
 <!-- Error definitions for p9_pm_occ_control procedure -->
+<!--
+     *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+     *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
+     *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+     *HWP Team: PM
+     *HWP Level: 3
+     *HWP Consumed by: HS
+-->
 <hwpErrors>
   <!-- ******************************************************************** -->
   <hwpError>
@@ -39,6 +40,16 @@
     that keeps it in the halt state.
     </description>
     <ffdc>JTAGCFG</ffdc>
+    <ffdc>TARGET</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>MEDIUM</priority>
+    </callout>
+    <collectRegisterFfdc>
+      <id>OCC_JTAG_FFDC_REGISTERS</id>
+      <target>TARGET</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    </collectRegisterFfdc>
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
@@ -49,5 +60,9 @@
     </description>
     <ffdc>ACTLENGTH</ffdc>
     <ffdc>LENGTH</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
   </hwpError>
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_sram_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_sram_init_errors.xml
index cf0c609ee..60c1bda74 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_sram_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_occ_sram_init_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -22,11 +22,24 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_pm_occ_sram_init procedure -->
+<!--
+     *HWP HWP Owner       : Greg Still <stillgs@us.ibm.com>
+     *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
+     *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+     *HWP Team            : PM
+     *HWP Level           : 3
+     *HWP Consumed by     : HS
+-->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PM_OCCSRAM_BAD_MODE</rc>
     <description>Unknown mode passed to p9_pm_occ_sram_init. </description>
     <ffdc>MODE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
   </hwpError>
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
index cb635129c..8eda96e2a 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
@@ -23,7 +23,14 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Register FFDC defintions used by all PM procedures -->
-
+<!--
+     *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+     *HWP HWP Backup Owner: Amit Kumar <akumar3@us.ibm.com>
+     *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+     *HWP Team: PM
+     *HWP Level: 3
+     *HWP Consumed by: SBE:HS:FSP
+-->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <registerFfdc>
@@ -174,4 +181,61 @@
     <scomRegister>PU_SPIPSS_P2S_WDATA_REG</scomRegister>
     <scomRegister>PU_SPIPSS_P2S_RDATA_REG</scomRegister>
   </registerFfdc>
+  <!-- ******************************************************************** -->
+  <registerFfdc>
+    <id>OCB_CHANNEL_FFDC_REGISTERS</id>
+    <scomRegister>PU_OCB_PIB_OCBAR0</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBAR1</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBAR2</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBAR3</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBDR0</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBDR1</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBDR2</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBDR3</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBCSR0_RO</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBCSR1_RO</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBCSR2_RO</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBCSR3_RO</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSHCS0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSHCS1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSHCS2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSHCS3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLCS0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLCS1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLCS2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLCS3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLBR0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLBR1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLBR2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSLBR3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSR0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSR1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSR2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSR3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWCR0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWCR1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWCR2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWCR3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSBR0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSBR1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSBR2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBLWSBR3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSES0_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSES1_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSES2_SCOM</scomRegister>
+    <scomRegister>PU_OCB_OCI_OCBSES3_SCOM</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBESR0</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBESR1</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBESR2</scomRegister>
+    <scomRegister>PU_OCB_PIB_OCBESR3</scomRegister>
+  </registerFfdc>
+  <!-- ******************************************************************** -->
+  <registerFfdc>
+      <id>OCC_JTAG_FFDC_REGISTERS</id>
+      <scomRegister>PU_JTG_PIB_OJIC_SCOM</scomRegister>
+      <scomRegister>PU_JTG_PIB_OJSTAT</scomRegister>
+      <scomRegister>PU_JTG_PIB_OJTDI</scomRegister>
+      <scomRegister>PU_JTG_PIB_OJTDO</scomRegister>
+      <scomRegister>PU_JTG_PIB_OJCFG</scomRegister>
+  </registerFfdc>
 </hwpErrors>